"A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation."

Swapnil Mhaske et al. (2015)

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DOI: 10.1109/SARNOF.2015.7324649

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-15

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Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic:
A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation. Sarnoff Symposium 2015: 88-93

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