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2020 – today
- 2023
[c24]Ko-Chi Kuo, Shih-En Huang, Hong-Yi Liao:
A 12-bit 1GS/s Digital to Analog Converter with Switching-Minimized Monotonic Coding. ICCE-Taiwan 2023: 217-218- [c23]Ko-Chi Kuo, Chao-Tung Chen, Hong-Yi Liao:
An Area Efficient Analog Front-End for Sensing EEG Signals with MOS Capacitors in 90nm Process. ICCE-Taiwan 2023: 255-256 - 2022
- [c22]Ko-Chi Kuo, Ying-Ju Sung:
A 12-bit 1 GS/s Current Steering DAC with the Appointed and Thermometer Coding Scheme. APCCAS 2022: 171-175 - [c21]Ko-Chi Kuo, Hsiung-Yu Chi:
A 8-bit 300MHz Domino Based Successive Approximation Register ADC. ISOCC 2022: 47-48 - 2021
- [c20]Ko-Chi Kuo:
A Fast Locking All Digital Delay Locked Loop with wide operating frequency ranged from 0.5 GHz to 1.8 GHz in 40nm Process. ISOCC 2021: 113-114 - [c19]Ko-Chi Kuo:
A Novel Linear-Logarithmic Active Pixel CMOS Image Sensor with wide dynamic range. MWSCAS 2021: 1100-1103
2010 – 2019
- 2019
- [c18]Hsu-Kang Dow
, Ing-Jer Huang, Robert Rieger, Ko-Chi Kuo, Lan-Yuen Guo, Shih-Jung Pao:
A Bio-Sensing System-on-Chip and Software for Smart Clothes. ICCE 2019: 1-4 - [c17]Ko-Chi Kuo:
Fast Locking Technique by Using a Programmable Operational Transconductor for a Phase Lock Loop Design. ICICDT 2019: 1-4 - [c16]Ko-Chi Kuo:
A High Speed Low Power Pipelined SAR Analog to Digital Converter. ICICDT 2019: 1-4 - [c15]Ko-Chi Kuo:
A 10-bit 250 MS/s Binary Search and Two channel SAR ADC by a two-bit per Conversion with Error Tolerance Ability. ISOCC 2019: 1-2 - 2016
- [c14]Ko-Chi Kuo:
The implementation of HomePlug AV system. ICICDT 2016: 1-4 - 2015
- [c13]Ko-Chi Kuo, Sz-Hsien Li:
A wide-range and harmonic-free SAR all-digital delay locked loop. ISCIT 2015: 197-200 - [c12]Ko-Chi Kuo, Chih-Wei Wu:
Power saving technique for thermometer-code digital-to-analog converters. ISCIT 2015: 205-208 - 2014
- [j6]Ko-Chi Kuo, Chi-Wei Wu:
A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX. Expert Syst. Appl. 41(2): 622-634 (2014) - 2012
- [j5]Ko-Chi Kuo, Yi-Hsi Hsu:
A 120-420 MHz delay-locked loop with multi-band voltage-controlled delay unit. Int. J. Circuit Theory Appl. 40(1): 49-63 (2012) - [c11]Ko-Chi Kuo, Chung-Yuan Chang, Si-Hsien Li:
Low power delay locked loop with all digital controlled SAR delay cell. APCCAS 2012: 120-123 - [c10]Ko-Chi Kuo, Shan-Yu Chen, Shih-Min Tseng:
High linear transconductor for multiband CMOS receiver. APCCAS 2012: 535-538 - [c9]Ko-Chi Kuo, Hsun-Chia Hsu:
Power line communication chip design with data error detecting/correcting and data encrypting/decrypting ability. ISPACS 2012: 674-677 - [c8]Ko-Chi Kuo, Hsueh-Ta Ko:
Low power design flow with static and statistical timing analysis. ISPACS 2012: 798-801 - 2011
- [j4]Ko-Chi Kuo:
A 2.4GHz low phase noise frequency synthesizer for WiMAX applications. IEICE Electron. Express 8(12): 938-943 (2011) - [j3]Ko-Chi Kuo, Chi-Wei Wu:
A Switching Sequence for Linear Gradient Error Compensation in the DAC Design. IEEE Trans. Circuits Syst. II Express Briefs 58-II(8): 502-506 (2011) - 2010
- [j2]Ko-Chi Kuo, Chi-Wen Chou:
Low power and high speed multiplier design with row bypassing and parallel architecture. Microelectron. J. 41(10): 639-650 (2010) - [c7]Ko-Chi Kuo, Sheng-Quane Chen:
Low power level shifter and combined with logic gates. APCCAS 2010: 324-327 - [c6]Ko-Chi Kuo, Jia-Wei Guo, Yu-Hao Ou:
A fully digital modulator/demodulator for Power Line Communication (PLC). APCCAS 2010: 835-838
2000 – 2009
- 2009
- [j1]Ko-Chi Kuo, Hsing-Hui Wu:
A low voltage, high linear, and tunable triode transconductor. IEICE Electron. Express 6(14): 1039-1044 (2009) - 2008
- [c5]Ko-Chi Kuo, Ming-Jing Chen:
5 GHz phase locked loop with auto band selection. APCCAS 2008: 550-553 - 2006
- [c4]Ko-Chi Kuo, Feng-Ji Wu:
A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-µm CMOS Technology. APCCAS 2006: 214-217 - [c3]Ko-Chi Kuo, Chi-Wen Chou:
Low Power Multiplier with Bypassing and Tree Strucuture. APCCAS 2006: 602-605 - [c2]Ko-Chi Kuo, Feng-Ji Wu:
A CMOS High-Speed Nine-Stage Programmable Counter. IMECS 2006: 213-216 - [c1]Ko-Chi Kuo, Chi-Wen Chou:
A Low-Power Multiplier with Bypassing Logic and Operand Decomposition. IMECS 2006: 217-220
Coauthor Index
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