"Low power and high speed multiplier design with row bypassing and parallel ..."

Ko-Chi Kuo, Chi-Wen Chou (2010)

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DOI: 10.1016/J.MEJO.2010.06.009

access: closed

type: Journal Article

metadata version: 2020-02-22

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Ko-Chi Kuo, Chi-Wen Chou:
Low power and high speed multiplier design with row bypassing and parallel architecture. Microelectron. J. 41(10): 639-650 (2010)

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