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ORCIDYaswanth K. Cherivirala
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Journal Articles
- 2023
[j1]Yaswanth K. Cherivirala
, David D. Wentzloff:
A Capacitor-Less Digital LDO Regulator With Synthesizable PID Controller Achieving 99.75% Efficiency and 93.3-ps Response Time in 65 nm. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1769-1773 (2023)
Conference and Workshop Papers
- 2024
- [c5]Yaswanth K. Cherivirala, David D. Wentzloff:
A Capacitor-less Hybrid LDO for Low Frequency Supply Noise Suppression Achieving 99.87% Efficiency and 3.32ps Response Time in 65nm. ISCAS 2024: 1-4 - [c4]Yaswanth Kumar Cherivirala, David D. Wentzloff:
A Technology-Agnostic Method for Digital LDO Synthesis and Layout Automation. ISLPED 2024: 1-6 - 2023
- [c3]Yaswanth K. Cherivirala, Mehdi Saligane, David D. Wentzloff:
An Open Source Compatible Framework to Fully Autonomous Digital LDO Generation. ISCAS 2023: 1-5 - 2020
- [c2]Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff:
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation. VLSI-SoC (Selected Papers) 2020: 65-85 - [c1]Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff:
An Open-source Framework for Autonomous SoC Design with Analog Block Generation. VLSI-SOC 2020: 141-146
Coauthor Index
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