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ORCIDJung-Woo Sull
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2020 – today
- 2024
[j3]Minkyo Shim
, Seungha Roh, Yunhee Lee, Jung-Woo Sull, Deog-Kyoon Jeong, Kwanseo Park:
A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3550-3560 (2024)- 2023
- [c4]Jung-Woo Sull, Minkyo Shim, Jung-Hun Park, Sanghee Lee, Deog-Kyoon Jeong:
An 8-GHz Octa-Phase Clock Corrector with Phase and Duty-Cycle Correction in 40-nm CMOS. MWSCAS 2023: 1005-1009 - 2022
- [j2]Jung-Woo Sull, Soyeong Shin, Jonghyun Oh, Kwang-Hoon Lee, Jihee Kim, Jung-Hun Park, Deog-Kyoon Jeong:
An 8-GHz Octa-Phase Error Corrector With Coprime Phase Comparison Scheme in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 874-878 (2022) - [c3]Jung-Hun Park, Kwang-Hoon Lee, Yongjae Lee, Jung-Woo Sull, Yoonho Song, Sanghee Lee, Hyeonseok Lee, Hoyeon Cho, Jonghyun Oh, Han-Gon Ko, Deog-Kyoon Jeong:
A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller. VLSI Technology and Circuits 2022: 150-151 - 2021
- [j1]Chang-Soo Yoon, Han-Gon Ko, Byung-Jun Kang, Jung-Woo Sull, Deog-Kyoon Jeong:
0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 136-140 (2021) - [c2]Hyungrok Do, Jung-Woo Sull, Seunghyun Lee, Kwangho Lee, Deog-Kyoon Jeong:
A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS. A-SSCC 2021: 1-3 - 2020
- [c1]Jung-Woo Sull, Hyungrok Do, Deog-Kyoon Jeong:
A 112-Gb/s PAM-4 Transmitter with 8: 1 MUX in 28-nm CMOS. ISOCC 2020: 266-267
Coauthor Index
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