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Journal Articles
- 2021
[j1]John Reuben
, Stefan Pechmann:
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1108-1121 (2021)
Conference and Workshop Papers
- 2024
- [c10]Stefan Pechmann, Eduardo Perez, Christian Wenger, Amelie Hagelauer:
A Current Mirror Based Read Circuit Design with Multi-Level Capability for Resistive Switching Devices. ICEIC 2024: 1-4 - [c9]Stefan Pechmann, Thorsten Spätling, Peter Reichel, Roland Müller, Amelie Hagelauer:
A Structured Approach for Embedded Memory Integration of Emerging Memory Technologies. LASCAS 2024: 1-5 - [c8]Running Guo, Stefan Pechmann, Amelie Hagelauer:
A Reading Method for 2T2R RRAM Arrays Coding their Multiple States. MWSCAS 2024: 157-161 - 2023
- [c7]Running Guo, Ruolan Jia, Stefan Pechmann, Marc Reichenbach, Amelie Hagelauer:
A High-speed Low-power Sense Amplifier for the RRAM Array with Multi-level Reading Function using 130-nm Technology. ICECS 2023: 1-4 - [c6]Ruolan Jia, Stefan Pechmann, Andrea Baroni, Christian Wenger, Amelie Hagelauer:
A RRAM Characterization System with Flexible Readout Operations using an Integrating ADC. PRIME 2023: 245-248 - 2022
- [c5]Stefan Pechmann, Amelie Hagelauer:
A Read Circuit Design for Multi-Level RRAM Cells Exhibiting Small Resistance Windows. MWSCAS 2022: 1-2 - [c4]Stefan Pechmann, Amelie Hagelauer:
A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays. SOCC 2022: 1-5 - 2021
- [c3]Markus Fritscher, Johannes Knödtel, Daniel Reiser, Maen Mallah, Stefan Pechmann, Dietmar Fey, Marc Reichenbach:
Simulating large neural networks embedding MLC RRAM as weight storage considering device variations. LASCAS 2021: 1-4 - [c2]Markus Fritscher, Johannes Knödtel, Maen Mallah, Stefan Pechmann, Emilio Pérez-Bosch Quesada, Tommaso Rizzi, Christian Wenger, Marc Reichenbach:
Mitigating the Effects of RRAM Process Variation on the Accuracy of Artificial Neural Networks. SAMOS 2021: 401-417 - 2020
- [c1]John Reuben, Stefan Pechmann:
A Parallel-friendly Majority Gate to Accelerate In-memory Computation. ASAP 2020: 93-100
Coauthor Index
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