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2010 – 2019
- 2010
[c2]Jürgen Pille, Dieter F. Wendel, Otto Wagner, Rolf Sautter, Wolfgang Penth, Thomas Fröhnel, Stefan Büttner, Otto A. Torreiter, Martin Eckert, Jose Paredes, David Hrusecky, David Ray, Miles G. Canada:
A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor. ISSCC 2010: 344-345
2000 – 2009
- 2006
- [c1]Erwin B. Cohen, Norman J. Rohrer, Peter A. Sandon, Miles G. Canada, Cédric Lichtenau, Mathew I. Ringler, Paul Kartschoke, Robert Floyd, Jan Heaslip, M. Ross, Thomas Pflueger, Rolf B. Hilgendorf, Pete McCormick, Gerard Salem, J. Connor, Stephen F. Geissler, Dana Thygesen:
A 64B CPU Pair: Dual- and Single-Processor Chips. ISSCC 2006: 333-342 - 2005
- [j2]Norman J. Rohrer, Cédric Lichtenau, Peter A. Sandon, Paul Kartschoke, Erwin B. Cohen, Miles G. Canada, Thomas Pflüger, Mathew I. Ringler, Rolf B. Hilgendorf, Stephen F. Geissler, Jeffrey S. Zimmerman:
A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features. IEEE J. Solid State Circuits 40(1): 19-27 (2005)
1990 – 1999
- 1998
- [j1]Chekib Akrout, John Bialas, Miles G. Canada, Duane Cawthron, James Corr, Bijan Davari, Robert Floyd, Stephen F. Geissler, Ronald Goldblatt, Robert Houle, Paul Kartschoke, Diane Kramer, Pete McCormick, Norman J. Rohrer, Gerard Salem, Ronald Schulz, Lisa Su, Linda Whitney:
A 480-MHz RISC microprocessor in a 0.12-μm Leff CMOS technology with copper interconnects. IEEE J. Solid State Circuits 33(11): 1609-1616 (1998)
Coauthor Index
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