"A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor."

Jürgen Pille et al. (2010)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2010.5433849

access: closed

type: Conference or Workshop Paper

metadata version: 2022-07-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/PilleWWSPFBTEPHRC10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/PilleWWSPFBTEPHRC10
Jürgen Pille, Dieter F. Wendel, Otto Wagner, Rolf Sautter, Wolfgang Penth, Thomas Fröhnel, Stefan Büttner, Otto A. Torreiter, Martin Eckert, Jose Paredes, David Hrusecky, David Ray, Miles G. Canada:
A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor. ISSCC 2010: 344-345

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.