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ORCIDZhangcheng Huang 0001
Person information
- affiliation: Fudan University, State Key Lab of Integrated Chips and Systems, Frontier Institute of Chip and System, Shanghai, China
Other persons with the same name
- Zhangcheng Huang 0002
![[0000-0001-6563-7668]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0001-6563-7668")
— Ping An Technology Co., Ltd., Shenzhen, China
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Journal Articles
- 2024
[j3]Jiarui Bao, Jinxin Zhang, Zhangcheng Huang, Zhaori Bi, Xingwei Feng, Xuan Zeng, Ye Lu:
Multiagent Based Reinforcement Learning (MA-RL): An Automated Designer for Complex Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4398-4411 (2024)- 2023
- [j2]Zhangcheng Huang:
Noise Model of Large-Format Readout Integrated Circuit for Infrared Focal Plane Array. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 142-153 (2023) - 2021
- [j1]Yunduo Li, Lianhua Ye, Xu Liu, Songlei Huang, Yingjie Ma, Zhangcheng Huang, Haimei Gong:
A Full CMOS Quenching Circuit With Fuse Protection for InGaAs/InP Single Photon Detectors. IEEE Trans. Circuits Syst. II Express Briefs 68(10): 3224-3228 (2021)
Conference and Workshop Papers
- 2024
- [c7]Jingyi Wang, Zhangcheng Huang, Bu Chen, Hongyang Shang, Jiapei Zheng, Hankun Lv, Chixiao Chen, Qi Liu, Ming Liu:
A 32×32 Flash LiDAR SPAD Sensor with Up-to-1kfps Motional Target Detection by Threshold-adaptive 2D Dynamic Vision. CICC 2024: 1-2 - [c6]Jiapei Zheng, Lizhou Wu, Yutong Su, Jingyi Wang, Zhangcheng Huang, Chixiao Chen, Qi Liu:
CAMPER: Exploring the Potential of Content Addressable Memory for 3D Point Cloud Efficient Range Search. DAC 2024: 129:1-129:6 - [c5]Bu Chen, Zhangcheng Huang, Qi Zheng, Weiyi Tang, Jingyi Wang, Hankun Lv, Chixiao Chen, Jianlu Wang, Qi Liu:
CEDAR: Computing-in-pixel Edge-aware Detection and Reconstruction Architecture for High-resolution 3D Imaging. DAC 2024: 217:1-217:6 - [c4]Bu Chen, Zhangcheng Huang, Qi Liu:
A 128×128 CMOS SPAD Receiver for 500Mbps Free Space Optical Communication with Column-wise Decoding and Fast Spot Tracking. ISCAS 2024: 1-5 - 2023
- [c3]Jinxin Zhang, Jiarui Bao, Zhangcheng Huang, Xuan Zeng, Ye Lu:
Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning. DAC 2023: 1-6 - [c2]Jiapei Zheng, Hao Jiang, Xinkai Nie, Zhangcheng Huang, Chixiao Chen, Qi Liu:
TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural Network. DAC 2023: 1-6 - [c1]Xinsheng Wang, Maosong Shi, Peizhe Li, Jianwei Liu, Zhangcheng Huang, Chixiao Chen, Wenning Jiang:
A 10b 1.25GS/s Residue Post-Amplified Pipelined-SAR ADC with Supply-and-Temperature Stabilized Open-Loop Residue Amplifier. ISCAS 2023: 1-5
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