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2020 – today
- 2024
[j4]Mohamed Megahed
, Yusang Chun, Zhiping Wang, Tejasvi Anand:
An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation. IEEE J. Solid State Circuits 59(8): 2492-2505 (2024)- 2023
- [c5]Henry Park, Mohammed Abdullatif, Ehung Chen, Ahmed Elmallah, Qaiser Nehal, Miguel Gandara, Tsz-Bin Liu, Amr Khashaba, Joonyeong Lee, Chih-Yi Kuan, Dhinessh Ramachandran, Ruey-Bo Sun, Atharav Atharav, Yusang Chun, Mantian Zhang, Deng-Fu Weng, Chung-Hsien Tsai, Chen-Hao Chang, Chia-Sheng Peng, Sheng-Tsung Hsu, Tamer A. Ali:
A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET. ISSCC 2023: 110-111 - 2022
- [j3]Yusang Chun, Mohamed Megahed, Ashwin Ramachandran, Tejasvi Anand:
A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS. IEEE J. Solid State Circuits 57(5): 1527-1541 (2022) - 2021
- [c4]Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand:
A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8. VLSI Circuits 2021: 1-2 - [c3]Zhiping Wang, Mohamed Megahed, Yusang Chun, Tejasvi Anand:
A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit. VLSI Circuits 2021: 1-2 - 2020
- [j2]Yusang Chun, Tejasvi Anand:
An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication - Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ/bit. IEEE J. Solid State Circuits 55(3): 567-579 (2020) - [j1]Ashwin Ramachandran, Yusang Chun, Mohamed Megahed, Tejasvi Anand:
An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS. IEEE J. Solid State Circuits 55(7): 1946-1959 (2020)
2010 – 2019
- 2019
- [c2]Yusang Chun, Tejasvi Anand:
A 13.6-16Gb/s Wireline Transceiver with Dicode Encoding and Sequence Detection Decoding for Equalizing 24.2dB with 2.56pJ/bit in 65nm CMOS. CICC 2019: 1-4 - [c1]Yusang Chun, Ashwin Ramachandran, Tejasvi Anand:
A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS. ESSCIRC 2019: 269-272
Coauthor Index
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