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2020 – today
- 2023
[c7]Marco Siracusa
, Víctor Soria Pardos, Francesco Sgherzi, Joshua Randall, Douglas J. Joseph, Miquel Moretó Planas, Adrià Armejach:
A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors. MICRO 2023: 1332-1346- [i3]Francesco Sgherzi, Marco Siracusa, Ivan Fernandez, Adrià Armejach, Miquel Moretó:
SpChar: Characterizing the Sparse Puzzle via Decision Trees. CoRR abs/2304.06944 (2023) - 2022
- [j3]Tan Nguyen, Colin MacLean, Marco Siracusa, Douglas Doerfler, Nicholas J. Wright, Samuel Williams:
FPGA-based HPC accelerators: An evaluation on performance and energy efficiency. Concurr. Comput. Pract. Exp. 34(20) (2022) - [j2]Marco Siracusa, Emanuele Del Sozzo, Marco Rabozzi, Lorenzo Di Tucci, Samuel Williams, Donatella Sciuto, Marco Domenico Santambrogio:
A Comprehensive Methodology to Optimize FPGA Designs via the Roofline Model. IEEE Trans. Computers 71(8): 1903-1915 (2022) - 2021
- [c6]Alberto Parravicini, Luca Giuseppe Cellamare, Marco Siracusa, Marco D. Santambrogio:
Scaling up HBM Efficiency of Top-K SpMV for Approximate Embedding Similarity on FPGAs. DAC 2021: 799-804 - [c5]Francesco Sgherzi, Alberto Parravicini, Marco Siracusa, Marco D. Santambrogio:
Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design. FCCM 2021: 78-87 - [c4]Douglas Doerfler, Farzad Fatollahi-Fard, Colin MacLean, Tan Nguyen, Samuel Williams, Nicholas J. Wright, Marco Siracusa:
Experiences Porting the SU3_Bench Microbenchmark to the Intel Arria 10 and Xilinx Alveo U280 FPGAs. IWOCL 2021: 1:1-1:9 - [i2]Alberto Parravicini, Luca Giuseppe Cellamare, Marco Siracusa, Marco Domenico Santambrogio:
Scaling up HBM Efficiency of Top-K SpMV for Approximate Embedding Similarity on FPGAs. CoRR abs/2103.04808 (2021) - [i1]Francesco Sgherzi, Alberto Parravicini, Marco Siracusa, Marco Domenico Santambrogio:
Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design. CoRR abs/2103.10040 (2021) - 2020
- [j1]Marco Siracusa, Fabrizio Ferrandi:
Tensor Optimization for High-Level Synthesis Design Flows. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 4217-4228 (2020) - [c3]Marco Siracusa, Marco Rabozzi, Emanuele Del Sozzo, Lorenzo Di Tucci, Samuel Williams, Marco D. Santambrogio:
A CAD-based methodology to optimize HLS code via the Roofline model. ICCAD 2020: 116:1-116:9 - [c2]Tan Nguyen, Samuel Williams, Marco Siracusa, Colin MacLean, Douglas Doerfler, Nicholas J. Wright:
The Performance and Energy Efficiency Potential of FPGAs in Scientific Computing. PMBS@SC 2020: 8-19
2010 – 2019
- 2019
- [c1]Marco Siracusa, Marco Rabozzi, Emanuele Del Sozzo, Marco D. Santambrogio, Lorenzo Di Tucci:
Automated Design Space Exploration and Roofline Analysis for FPGA-Based HLS Applications. FCCM 2019: 314
Coauthor Index
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