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ORCIDS. S. Teja Nibhanupudi
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2020 – today
- 2023
[c5]S. S. Teja Nibhanupudi, Sirish Oruganti
, Rahul Mathur, Nishant Gupta, Meizhi Wang, Jaydeep P. Kulkarni:
Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges. DAC 2023: 1-4- 2022
- [j3]Siddhartha Raman Sundara Raman, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni:
Enabling In-Memory Computations in Non-Volatile SRAM Designs. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 557-568 (2022) - [c4]Rishab Mehra, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni:
Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation. DRC 2022: 1-2 - [c3]S. S. Teja Nibhanupudi, Dmitry Veksler, Anupam Roy, Matthew Coupin, Kevin C. Matthews, Jamie Warner, Gennadi Bersuker, Jaydeep P. Kulkarni, Sanjay Kumar Banerjee:
Experimental demonstration of sub-nanosecond switching in 2D hexagonal Boron Nitride resistive memory devices. DRC 2022: 1-2 - 2021
- [j2]Aseem Sayal, Shirin Fathima, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni:
COMPAC: Compressed Time-Domain, Pooling-Aware Convolution CNN Engine With Reduced Data Movement for Energy-Efficient AI Computing. IEEE J. Solid State Circuits 56(7): 2205-2220 (2021) - 2020
- [j1]Aseem Sayal, S. S. Teja Nibhanupudi, Shirin Fathima, Jaydeep P. Kulkarni:
A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing. IEEE J. Solid State Circuits 55(1): 60-75 (2020)
2010 – 2019
- 2019
- [c2]Jacob N. Rohan, Pingping Zhuang, S. S. Teja Nibhanupudi, Sanjay Kumar Banerjee, Jaydeep P. Kulkarni:
Neural Network Assisted Compact Model for Accurate Characterization of Cycle-to-cycle Variations in 2-D $h$-BN based RRAM devices. DRC 2019: 103-104 - [c1]Aseem Sayal, Shirin Fathima, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni:
All-Digital Time-Domain CNN Engine Using Bidirectional Memory Delay Lines for Energy-Efficient Edge Computing. ISSCC 2019: 228-230
Coauthor Index
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