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2020 – today
- 2022
[i1]Cameron Haigh, Zichen Zhang, Negar Hassanpour, Khurram Javed, Yingying Fu, Shayan Shahramian, Shawn Zhang, Jun Luo:
Drawing Inductor Layout with a Reinforcement Learning Agent: Method and Application for VCO Inductors. CoRR abs/2202.11798 (2022)- 2021
- [c5]Ming Yang, Shayan Shahramian, Henry Wong, Peter Krotnev, Anthony Chan Carusone:
Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers. ISCAS 2021: 1-5 - 2020
- [j5]Ming Yang
, Shayan Shahramian, Hossein Shakiba, Henry Wong, Peter Krotnev, Anthony Chan Carusone:
Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 284-297 (2020)
2010 – 2019
- 2019
- [c4]Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto:
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. ISSCC 2019: 482-484 - 2016
- [j4]Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone:
Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5~µs. IEEE J. Solid State Circuits 51(12): 3192-3203 (2016) - [c3]Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone:
23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs. ISSCC 2016: 410-411 - 2015
- [j3]Shayan Shahramian, Anthony Chan Carusone:
A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS. IEEE J. Solid State Circuits 50(7): 1722-1735 (2015) - [j2]Shayan Shahramian, Anthony Chan Carusone:
Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS". IEEE J. Solid State Circuits 50(10): 2463 (2015) - 2014
- [c2]Shayan Shahramian, Anthony Chan Carusone:
A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS. ESSCIRC 2014: 439-442 - 2012
- [j1]Shayan Shahramian, Hemesh Yasotharan, Anthony Chan Carusone:
Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters. IEEE Trans. Circuits Syst. II Express Briefs 59-II(6): 326-330 (2012) - 2011
- [c1]Shayan Shahramian, Clifford Ting, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune:
A pattern-guided adaptive equalizer in 65nm CMOS. ISSCC 2011: 354-356
Coauthor Index
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