"Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE ..."

Shayan Shahramian, Anthony Chan Carusone (2015)

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DOI: 10.1109/JSSC.2015.2470855

access: closed

type: Journal Article

metadata version: 2020-08-30

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Shayan Shahramian, Anthony Chan Carusone:
Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS". IEEE J. Solid State Circuits 50(10): 2463 (2015)

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