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2020 – today
- 2024
[j5]Francesco Vigli, Marcello Barbirotta
, Abdallah Cheikh, Francesco Menichelli, Antonio Mastrandrea, Mauro Olivieri:
A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection. IEEE Access 12: 30495-30506 (2024)- [j4]Marcello Barbirotta, Francesco Menichelli, Abdallah Cheikh, Antonio Mastrandrea, Marco Angioli, Mauro Olivieri:
Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems. IEEE Access 12: 95720-95735 (2024) - [j3]Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri:
Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme. IEEE Trans. Computers 73(7): 1767-1779 (2024) - [c14]Marco Angioli, Saeid Jamili, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Antonello Rosato, Mauro Olivieri:
AeneasHDC: An Automatic Framework for Deploying Hyperdimensional Computing Models on FPGAs. IJCNN 2024: 1-8 - [c13]Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Mauro Olivieri:
Exploring Variable Latency Dividers in Vector Hardware Accelerators. PRIME 2024: 1-4 - 2023
- [c12]Marcello Barbirotta, Francesco Menichelli, Antonio Mastrandrea, Abdallah Cheikh, Marco Angioli, Saeid Jamili, Mauro Olivieri:
Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects. ApplePies 2023: 15-21 - [c11]Saeid Jamili, Antonio Mastrandrea, Abdallah Cheikh, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri:
A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach. ApplePies 2023: 36-41 - [c10]Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Saeid Jamili, Francesco Menichelli, Mauro Olivieri:
Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design. ApplePies 2023: 42-48 - 2022
- [j2]Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri:
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors. IEEE Access 10: 126074-126088 (2022) - [c9]Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri:
Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators. ApplePies 2022: 149-154 - [c8]Saeid Jamili, Abdallah Cheikh, Antonio Mastrandrea, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri:
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. ApplePies 2022: 300-306 - [c7]Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri:
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration. PRIME 2022: 237-240 - 2021
- [j1]Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri:
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores. IEEE Micro 41(2): 64-71 (2021) - [c6]Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri:
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. DFT 2021: 1-4 - 2020
- [b1]Abdallah Cheikh:
Energy-efficient digital electronic systems design for edge-computing applications, through innovative RISC-V compliant processors. Sapienza University of Rome, Italy, 2020 - [c5]Marcello Barbirotta, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Luigi Blasi, Abdallah Cheikh, Stefano Sordillo, Fabio Di Gennaro, Mauro Olivieri:
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment. DFT 2020: 1-6 - [i2]Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri:
Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores. CoRR abs/2007.09109 (2020)
2010 – 2019
- 2019
- [c4]Luigi Blasi, Francesco Vigli, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri:
A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. ApplePies 2019: 505-511 - [c3]Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri:
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor. ApplePies 2019: 529-539 - 2017
- [c2]Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri:
The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes. ApplePies 2017: 89-97 - [c1]Mauro Olivieri, Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli:
Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores. NGCAS 2017: 45-48 - [i1]Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri:
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes. CoRR abs/1712.04902 (2017)
Coauthor Index
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last updated on 2024-10-07 22:24 CEST by the dblp team
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