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ORCIDGuilhem Larrieu
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2020 – today
- 2024
[c8]Ian O'Connor, Sara Mannaa, Alberto Bosio, Bastien Deveautour, Damien Deleruyelle, Tetiana Obukhova, Cédric Marchand, Jens Trommer, Çigdem Çakirlar, Bruno Neckel Wesling, Thomas Mikolajick, Oskar Baumgartner, Mischa Thesberg, David Pirker, Christoph Lenz, Zlatan Stanojevic, Markus Karner, Guilhem Larrieu, Sylvain Pelloquin, Konstantinous Moustakas, Jonas Müller, Giovanni Ansaloni, Alireza Amirshahi, David Atienza, Jean-Luc Rouas, Leila Ben Letaifa, Georgeta Bordeall, Charles Brazier, Chhandak Mukherjee, Marina Deng, Yifan Wang, Marc François, Houssem Rezgui
, Reveil Lucas, Cristell Maneux:
FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation. DATE 2024: 1-6- 2023
- [c7]Yifan Wang, Chhandak Mukherjee, Houssem Rezgui, Marina Deng, Cristell Maneux, Sara Mannaa, Ian O'Connor, Jonas Müller, Sylvain Pelloquin, Guilhem Larrieu:
Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design. ESSDERC 2023: 57-60 - 2022
- [c6]Arnaud Poittevin, Ian O'Connor, Cédric Marchand, Alberto Bosio, Cristell Maneux, Chhandak Mukherjee, Guilhem Larrieu, Abhishek Kumar:
A Logic Cell Design and routing Methodology Specific to VNWFET. NEWCAS 2022: 460-464 - [c5]Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O'Connor, Oskar Baumgartner, David Pirker:
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors. VLSI-SoC 2022: 1-2 - 2020
- [c4]Chhandak Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Cédric Marchand, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu:
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. VLSI-SOC 2020: 76-81 - [c3]Arnaud Poittevin, Chhandak Mukherjee, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng, Sébastien Le Beux, François Marc, Aurélie Lecestre, Cédric Marchand, Abhishek Kumar:
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. VLSI-SoC (Selected Papers) 2020: 301-321 - [i2]C. Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu:
3D logic cells design and results based on Vertical NWFET technology including tied compact model. CoRR abs/2005.14039 (2020)
2010 – 2019
- 2018
- [i1]Peter R. Wiecha, Aurélie Lecestre, Nicolas Mallet, Guilhem Larrieu:
Pushing the limits of optical information storage using deep learning. CoRR abs/1805.03468 (2018) - 2017
- [c2]Chhandak Mukherjee, Cristell Maneux, Julien Pezard, Guilhem Larrieu:
1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors. ESSDERC 2017: 34-37 - 2015
- [c1]Guilhem Larrieu, Y. Guerfi, X. L. Han, N. Clement:
Vertical field effect transistor with sub-15nm gate-all-around on Si nanowire array. ESSDERC 2015: 202-205
Coauthor Index
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