"Electrothermal modeling of junctionless vertical Si nanowire transistors ..."

Yifan Wang et al. (2023)

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DOI: 10.1109/ESSDERC59256.2023.10268560

access: closed

type: Conference or Workshop Paper

metadata version: 2023-10-09

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Yifan Wang, Chhandak Mukherjee, Houssem Rezgui, Marina Deng, Cristell Maneux, Sara Mannaa, Ian O'Connor, Jonas Müller, Sylvain Pelloquin, Guilhem Larrieu:
Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design. ESSDERC 2023: 57-60

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