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ORCIDWarin Sootkaneung
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2020 – today
- 2021
[c15]Warin Sootkaneung
, Sasithorn Chookaew, Suppachai Howimanporn:
Temperature-Aware Evaluation and Mitigation of Logic Soft Errors Under Circuit Variations. ATS 2021: 31-36
2010 – 2019
- 2019
- [c14]Sasithorn Chookaew, Suppachai Howimanporn, Warin Sootkaneung:
A Practical Technology-Enhanced Approach for Programmable Logic Controller (PLC) Training Course. ICETC 2019: 115-119 - 2018
- [j1]Warin Sootkaneung, Suppachai Howimanporn, Sasithorn Chookaew:
Temperature effects on BTI and soft errors in modern logic circuits. Microelectron. Reliab. 87: 259-270 (2018) - [c13]Sasithorn Chookaew, Suppachai Howimanporn, Pornjit Pratumsuwan, Santi Hutamarn, Warin Sootkaneung, Charoenchai Wongwatkit:
Enhancing High-School Students' Computational Thinking with Educational Robotics Learning. IIAI-AAI 2018: 204-208 - [c12]Suppachai Howimanporn, Sasithorn Chookaew, Warin Sootkaneung:
Implementation of Swarm Based Gain Scheduling for 2D Inverted Pendulum Using PLC. IIAI-AAI 2018: 630-633 - 2017
- [c11]Warin Sootkaneung, Suppachai Howimanporn, Sasithorn Chookaew:
Thermal Effect on Performance, Power, and BTI Aging in FinFET-Based Designs. DSD 2017: 345-351 - [c10]Sasithorn Chookaew, Suppachai Howimanporn, Warin Sootkaneung, Charoenchai Wongwatkit:
Motivating Pre-service Teachers with Augmented Reality to Developing Instructional Materials through Project-Based Learning Approach. IIAI-AAI 2017: 780-784 - 2016
- [c9]Warin Sootkaneung, Sasithorn Chookaew, Suppachai Howimanporn:
Combined Impact of BTI and Temperature Effect Inversion on Circuit Performance. ATS 2016: 310-315 - [c8]Warin Sootkaneung, Pipatphon Lapamonpinyo, Sasithorn Chookaew, Suppachai Howimanporn:
NBTI in FinFET Circuits under the Temperature Effect Inversion. CSE/EUC/DCABES 2016: 343-350 - [c7]Suppachai Howimanporn, Sunphong Thanok, Sasithorn Chookaew, Warin Sootkaneung:
Design and implementation of PSO based LQR control for inverted pendulum through PLC. SII 2016: 664-669 - [c6]Suppachai Howimanporn, Sunphong Thanok, Sasithorn Chookaew, Warin Sootkaneung:
Speed control technique for conveyor using PSO based PID with programmable logic controller. SII 2016: 670-675 - 2012
- [c5]Warin Sootkaneung, Kewal K. Saluja:
Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate. VLSI Design 2012: 74-79 - 2011
- [c4]Warin Sootkaneung, Kewal K. Saluja:
Soft error reduction through gate input dependent weighted sizing in combinational circuits. ISQED 2011: 603-610 - 2010
- [c3]Warin Sootkaneung, Kewal K. Saluja:
Gate input reconfiguration for combating soft errors in combinational circuits. DSN Workshops 2010: 107-112 - [c2]Warin Sootkaneung, Kewal K. Saluja:
On techniques for handling soft errors in digital circuits. ITC 2010: 744-752
2000 – 2009
- 2008
- [c1]Kewal K. Saluja, Shriram Vijayakumar, Warin Sootkaneung, Xaingning Yang:
NBTI Degradation: A Problem or a Scare? VLSI Design 2008: 137-142
Coauthor Index
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