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2010 – 2019
- 2016
[c5]Jeffrey Prinzie
, Michiel Steyaert, Paul Leroux, Jorgen Christiansen, Paulo Moreira:
A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS. A-SSCC 2016: 285-288- 2015
- [c4]Sara Marconi, Elia Conti, Pisana Placidi, Andrea Scorzoni, Jorgen Christiansen, Tomasz Hemperek:
A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications. ApplePies 2015: 35-41 - [c3]Sara Marconi, Elia Conti, Jorgen Christiansen, Pisana Placidi:
Reusable SystemVerilog-UVM design framework with constrained stimuli modeling for High Energy Physics applications. ISSE 2015: 391-397 - 2013
- [c2]Lukas Perktold, Jorgen Christiansen:
A fine time-resolution (<3 ps-rms) time-to-digital converter for highly integrated designs. I2MTC 2013: 1092-1097
1990 – 1999
- 1999
- [j2]Manuel Mota, Jorgen Christiansen:
A high-resolution time interpolator based on a delay locked loop and an RC delay line. IEEE J. Solid State Circuits 34(10): 1360-1366 (1999) - 1998
- [c1]Manuel Mota, Jorgen Christiansen:
A four channel, self-calibrating, high resolution, time to digital converter. ICECS 1998: 409-412 - 1996
- [j1]Jorgen Christiansen:
An integrated high resolution CMOS timing generator based on an array of delay locked loops. IEEE J. Solid State Circuits 31(7): 952-957 (1996)
Coauthor Index
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