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Jose Raul Garcia Ordaz

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2010 – 2019

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2018
[b1]
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Jose Raul Garcia Ordaz:
Dynamic CPU ISA customizations through FPGA interlays. University of Manchester, UK, 2018
[c5]
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Jose Raul Garcia Ordaz, Dirk Koch:
A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine. ASAP 2018: 1-8
2017
[c4]
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Jose Raul Garcia Ordaz, Dirk Koch:
Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit. FPL 2017: 1-4
[c3]
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Anuj Vaishnav, Jose Raul Garcia Ordaz, Dirk Koch:
A security library for FPGA interlays. FPL 2017: 1-4
[c2]
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Jose Raul Garcia Ordaz, Dirk Koch:
HLS Compilation for CPU Interlays. HEART 2017: 27:1-27:6
2016
[c1]
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Jose Raul Garcia Ordaz, Dirk Koch:
soft-NEON: A study on replacing the NEON engine of an ARM SoC with a reconfigurable fabric. ASAP 2016: 229-230
2012
[j1]
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  - electronic edition @ ipn.mx (open access)
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  - journals/cys/OrdazRVLM12
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Jose Raul Garcia Ordaz, Marco Antonio Ramírez Salinas, Luis A. Villa Vargas, Herón Molina Lozano, Cuauhtémoc Peredo Macías:
A Reorder Buffer Design for High Performance Processors. Computación y Sistemas 16(1) (2012)

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