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ORCIDSrinivas Jallepalli
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2020 – today
- 2024
[c1]Srinivas Jallepalli
:
Machine Learning for High Sigma Analog Designs (Invited). MLCAD 2024: 37:1-37:6
2010 – 2019
- 2016
- [j5]Srinivas Jallepalli, Ram Mooraka, Sanjay Parihar, Earl Hunter, Elie Maalouf:
Employing Scaled Sigma Sampling for Efficient Estimation of Rare Event Probabilities in the Absence of Input Domain Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(6): 943-956 (2016) - [j4]Srinivas Jallepalli, Ram Mooraka, Sanjay Parihar, Earl Hunter, Elie Maalouf:
Rapid Assessment of Design Sensitivity to Process Excursions via Scaled Sigma Sampling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(6): 957-970 (2016)
1990 – 1999
- 1998
- [j3]Wei-Kai Shih, Srinivas Jallepalli, C.-F. Yeap, Mahbub Rashed, Christine M. Maziar, A. F. Tasch Jr.:
A Monte Carlo Study of Electron Transport in Silicon nMOSFET Inversion Layers. VLSI Design 6(1-4): 53-56 (1998) - [j2]Mahbub Rashed, Wei-Kai Shih, Srinivas Jallepalli, R. Zaman, Thomas J. T. Kwan, Christine M. Maziar:
A Monte Carlo study , of Electron Transport in Strained Si/SiGe Heterostructures. VLSI Design 6(1-4): 213-216 (1998) - [j1]Wei-Kai Shih, Srinivas Jallepalli, Mahbub Rashed, Christine M. Maziar, A. F. Tasch Jr.:
Study of Electron Velocity Overshoot in NMOS Inversion Layers. VLSI Design 8(1-4): 429-435 (1998)
Coauthor Index
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