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ORCIDLembit Jürimägi
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Journal Articles
- 2020
[j3]Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs. Microprocess. Microsystems 77: 103117 (2020)- 2018
- [j2]Raimund Ubar
, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Lembit Jürimägi:
Fast identification of true critical paths in sequential circuits. Microelectron. Reliab. 81: 252-261 (2018) - 2017
- [j1]Raimund Ubar, Lembit Jürimägi, Jaan Raik, Vladimir Viies:
Modeling and simulation of circuits with shared structurally synthesized BDDs. Microprocess. Microsystems 48: 56-61 (2017)
Conference and Workshop Papers
- 2024
- [c10]Tarmo Robal, Uljana Reinsalu, Janika Leoste, Lembit Jürimägi, Risto Heinsar:
Teaching Rapid Application Development Skills for Digitalisation Challenges. DB&IS 2024: 177-192 - 2019
- [c9]Raimund Ubar, Lembit Jürimägi, Adeniyi Olanrewaju Adekoya, Maksim Jenihhin:
True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits. DSD 2019: 492-499 - [c8]Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Adeboye Stephen Oyeniran:
Application Specific True Critical Paths Identification in Sequential Circuits. IOLTS 2019: 299-304 - [c7]Lembit Jürimägi, Raimund Ubar, Vladimir Viies:
Equivalent Transformations of Structurally Synthesized BDDs and Applications. MECO 2019: 1-6 - 2018
- [c6]Raimund Ubar, Lembit Jurimagi, Maksim Jenihhin, Jaan Raik, Niyi-Leigh Olugbenga, Vladimir Viies:
Timing-critical path analysis with structurally synthesized BDDs. MECO 2018: 1-6 - [c5]Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin:
Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. PATMOS 2018: 1-6 - 2015
- [c4]Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Galina Josifovska, Stephen Adeboye Oyeniran:
Double Phase Fault Collapsing with Linear Complexity in Digital Circuits. DSD 2015: 700-705 - [c3]Raimund Ubar, Lembit Jurimagi, Jaan Raik:
Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits. NORCAS 2015: 1-4 - [c2]Raimund Ubar, Lembit Jürimägi, Elmet Orasson, Jaan Raik:
Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs. VLSI-SoC (Selected Papers) 2015: 23-45 - [c1]Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Jaan Raik:
Scalable algorithm for structural fault collapsing in digital circuits. VLSI-SoC 2015: 171-176
Coauthor Index
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