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Sandipan Sinha

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2020 – today

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2024
[c4]
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  dblp key:
  - conf/vlsid/SinhaTSEGHG24
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Sandipan Sinha, Manish Trivedi, Jaswinder Singh, Sriharsha Enjapuri, Deepesh Gujjar, Ramesh Halli, Girishankar Gurumurthy:
A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range. VLSID 2024: 84-89
2023
[c3]
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Sandipan Sinha, Manish Trivedi, Jaswinder Singh, Sriharsha Enjapuri, Deepesh Gujjar, Ramesh Halli, Girishankar Gurumurthy:
An Innovative Write Circuitry for Enhancing a 3nm L1 Cache Performance Across Wide DVFS Range. APCCAS 2023: 375-377
2021
[c2]
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Sriharsha Enjapuri, Deepesh Gujjar, Sandipan Sinha, Ramesh Halli, Manish Trivedi:
A 5nm Wide Voltage Range Ultra High Density SRAM Design for L2/L3 Cache Applications. VLSID 2021: 151-156

2010 – 2019

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2014
[c1]
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Kaushik Lahiri, Avirup Mandal, Sandipan Sinha, Amitava Mukherjee:
Wireless personal health ECG monitoring application. WPMC 2014: 618-623

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