"A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range."

Sandipan Sinha et al. (2024)

> Home

Details and statistics

DOI: 10.1109/VLSID60093.2024.00019

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-08

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsid/SinhaTSEGHG24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/SinhaTSEGHG24
Sandipan Sinha, Manish Trivedi, Jaswinder Singh, Sriharsha Enjapuri, Deepesh Gujjar, Ramesh Halli, Girishankar Gurumurthy:
A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range. VLSID 2024: 84-89

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.