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2020 – today
- 2024
[j7]Willian Analdo Nunes
, Rafael Schild Reusch, Lucas Luza, Eduardo Bernardon, Angelo Elias Dalzotto, Leonardo Rezende Juracy, Fernando Gehm Moraes:
Deploying human activity recognition in embedded RISC-V processors. Des. Autom. Embed. Syst. 28(3): 187-217 (2024)- 2023
- [j6]Leonardo Rezende Juracy, Rafael Garibotti, Fernando Gehm Moraes:
From CNN to DNN Hardware Accelerators: A Survey on Design, Exploration, Simulation, and Frameworks. Found. Trends Electron. Des. Autom. 13(4): 270-344 (2023) - [j5]Leonardo Rezende Juracy, Alexandre M. Amory, Fernando Moraes:
A Comprehensive Evaluation of Convolutional Hardware Accelerators. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1149-1153 (2023) - [c10]Rafael Schild Reusch, Leonardo Rezende Juracy, Fernando Gehm Moraes:
Deploying Machine Learning in Resource-Constrained Devices for Human Activity Recognition. SBESC 2023: 1-6 - 2022
- [j4]Leonardo Rezende Juracy, Alexandre de Morais Amory, Fernando Gehm Moraes:
A Fast, Accurate, and Comprehensive PPA Estimation of Convolutional Hardware Accelerators. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 5171-5184 (2022) - [c9]Rafael Schild Reusch, Leonardo Rezende Juracy, Fernando Gehm Moraes:
Assessment and Optimization of 1D CNN Model for Human Activity Recognition. SBESC 2022: 1-7 - 2021
- [j3]Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Alexandre F. Hampel, Fernando Gehm Moraes:
A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators. IEEE Trans. Circuits Syst. I Regul. Pap. 68(11): 4783-4795 (2021) - [c8]Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory, Fernando Gehm Moraes:
A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators. LASCAS 2021: 1-4 - 2020
- [c7]Felipe A. Kuentzer, Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory:
Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template. ASYNC 2020: 86-93 - [i1]Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Fernando Gehm Moraes:
A Survey of Aging Monitors and Reconfiguration Techniques. CoRR abs/2007.07829 (2020)
2010 – 2019
- 2018
- [j2]Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Alexandre M. Amory:
A DfT Insertion Methodology to Scannable Q-Flop Elements. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1609-1612 (2018) - [c6]Felipe A. Kuentzer, Leonardo Rezende Juracy, Alexandre M. Amory:
On the reuse of timing resilient architecture for testing path delay faults in critical paths. DATE 2018: 379-384 - [c5]Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Fernando Gehm Moraes, Alexandre M. Amory:
An LSSD Compliant Scan Cell for Flip-Flops. ISCAS 2018: 1-5 - [c4]Felipe A. Kuentzer, Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory:
Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template. SBCCI 2018: 1-6 - 2017
- [j1]Leonardo Rezende Juracy, Matheus Trevisan Moreira, Felipe Augusto Kuentzer, Alexandre de Morais Amory:
Optimized Design of an LSSD Scan Cell. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 765-768 (2017) - [c3]Leonardo Rezende Juracy, Felipe B. Lazzarotto, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
XGT4: An industrial grade, open source tester for multi-gigabit networks. ICECS 2017: 252-255 - 2014
- [c2]Eduardo Wächter, Augusto Erichsen, Leonardo Juracy, Alexandre M. Amory, Fernando Moraes:
Runtime fault recovery protocol for NoC-based MPSoCs. ISQED 2014: 132-139 - [c1]Eduardo Wächter, Augusto Erichsen, Leonardo Juracy, Alexandre M. Amory, Fernando Gehm Moraes:
A Fast Runtime Fault Recovery Approach for NoC-Based MPSoCS for Performance Constrained Applications. SBCCI 2014: 18:1-18:7
Coauthor Index
aka: Alexandre de Morais Amory
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