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ORCIDMasanori Muroyama
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2020 – today
- 2021
[j8]Joerg Froemel
, Gildas Diguet, Masanori Muroyama:
Micromechanical Force Sensor Using the Stress-Impedance Effect of Soft Magnetic FeCuNbSiB. Sensors 21(22): 7578 (2021)- 2020
- [j7]Masanori Muroyama, Hideki Hirano, Chenzhong Shao, Shuji Tanaka:
Development of a Real-Time Force and Temperature Sensing System with MEMS-LSI Integrated Tactile Sensors for Next-Generation Robots. J. Robotics Mechatronics 32(2): 323-332 (2020)
2010 – 2019
- 2018
- [j6]Chenzhong Shao, Shuji Tanaka, Takahiro Nakayama, Yoshiyuki Hata, Masanori Muroyama:
Electrical Design and Evaluation of Asynchronous Serial Bus Communication Network of 48 Sensor Platform LSIs with Single-Ended I/O for Integrated MEMS-LSI Sensors. Sensors 18(1): 231 (2018) - [j5]Mitsutoshi Makihata, Masanori Muroyama, Shuji Tanaka, Takahiro Nakayama, Yutaka Nonomura, Masayoshi Esashi:
Design and Fabrication Technology of Low Profile Tactile Sensor with Digital Interface for Whole Body Robot Skin. Sensors 18(7): 2374 (2018) - 2017
- [j4]Chenzhong Shao, Shuji Tanaka, Takahiro Nakayama, Yoshiyuki Hata, Travis Bartley, Yutaka Nonomura, Masanori Muroyama:
A Tactile Sensor Network System Using a Multiple Sensor Platform with a Dedicated CMOS-LSI for Robot Applications. Sensors 17(9): 1974 (2017) - [j3]Sho Asano, Masanori Muroyama, Takahiro Nakayama, Yoshiyuki Hata, Yutaka Nonomura, Shuji Tanaka:
3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer. Sensors 17(11): 2451 (2017) - 2016
- [c11]Chenzhong Shao, Takahiro Nakayama, Yoshiyuki Hata, Travis Bartley, Yutaka Nonomura, Shuji Tanaka, Masanori Muroyama:
A multiple sensor platform with dedicated CMOS-LSIs for robot applications. NEMS 2016: 245-250 - [c10]Naokatsu Ikegami, Takashi Yoshida, Akira Kojima, Hiroshi Miyaguchi, Masanori Muroyama, Shinya Yoshida, Kentaro Totsu, Nobuyoshi Koshida, Masayoshi Esashi:
Fabrication of through silicon via with highly phosphorus-doped polycrystalline Si plugs for driving an active-matrix nanocrystalline Si electron emitter array. NEMS 2016: 578-582 - 2015
- [c9]Travis Bartley, Shuji Tanaka, Yutaka Nonomura, Takahiro Nakayama, Masanori Muroyama:
Delay window blind oversampling clock and data recovery algorithm with wide tracking range. ISCAS 2015: 1598-1601
2000 – 2009
- 2008
- [c8]Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura:
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. PATMOS 2008: 62-71 - [c7]Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato:
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. SASP 2008: 83-88 - 2006
- [c6]Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah:
An Energy Characterization Framework for Software-Based Embedded Systems. ESTIMedia 2006: 59-64 - [c5]Makoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto:
A Simulation-Based Soft Error Estimation Methodology for Computer Systems. ISQED 2006: 196-203 - 2005
- [j2]Kosuke Tarumi, Akihiko Hyodo, Masanori Muroyama, Hiroto Yasuura:
Bitwidth Optimization for Low Power Digital FIR Filter Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 869-875 (2005) - [c4]Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura:
A variation-aware low-power coding methodology for tightly coupled buses. ASP-DAC 2005: 557-560 - 2003
- [j1]Akihiko Hyodo, Masanori Muroyama, Hiroto Yasuura:
Variable Pipeline Depth Processor for Energy Efficient Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2983-2990 (2003) - [c3]Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura:
A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits. DSD 2003: 408-415 - 2002
- [c2]Takanori Okuma, Yun Cao, Masanori Muroyama, Hiroto Yasuura:
Reducing access energy of on-chip data memory considering active data bitwidth. ISLPED 2002: 88-91 - [c1]Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura:
A Power Minimization Technique for Arithmetic Circuits by Cell Selection. ASP-DAC/VLSI Design 2002: 268-273
Coauthor Index
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