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2010 – 2019
- 2019
[j7]Hongda Xu
, Hai Huang, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu:
A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS. IEEE J. Solid State Circuits 54(2): 441-451 (2019)- [j6]Yuan Zhou, Benwei Xu, Yun Chiu:
A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC. IEEE J. Solid State Circuits 54(8): 2207-2218 (2019) - 2017
- [j5]Benwei Xu, Yuan Zhou, Yun Chiu:
A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS. IEEE J. Solid State Circuits 52(4): 1091-1100 (2017) - [c7]Hongda Xu, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu:
28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS. ISSCC 2017: 476-477 - [c6]Sudipta Sarkar, Benwei Xu, Brian Elies, Yun Chiu:
An 8b 1.39GS/S 0.85V two-step ADC with background comparator offset calibration. MWSCAS 2017: 591-594 - 2016
- [j4]Shuang Zhu, Benwei Xu, Bo Wu, Kiran Soppimath, Yun Chiu:
A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM. IEEE J. Solid State Circuits 51(8): 1785-1796 (2016) - [j3]Bo Wu, Shuang Zhu, Benwei Xu, Yun Chiu:
A 24.7 mW 65 nm CMOS SAR-Assisted CT ΔΣ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR. IEEE J. Solid State Circuits 51(12): 2893-2905 (2016) - [c5]Bo Wu, Shuang Zhu, Benwei Xu, Yun Chiu:
15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS. ISSCC 2016: 270-271 - [c4]Benwei Xu, Yuan Zhou, Yun Chiu:
A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j2]Yuan Zhou, Benwei Xu, Yun Chiu:
A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector. IEEE J. Solid State Circuits 50(4): 920-931 (2015) - [j1]Benwei Xu, Yun Chiu:
Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1306-1314 (2015) - [c3]Shuang Zhu, Benwei Xu, Bo Wu, Kiran Soppimath, Yun Chiu:
A 0.073-mm2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM. CICC 2015: 1-4 - 2014
- [c2]Yuan Zhou, Benwei Xu, Yun Chiu:
A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration. VLSIC 2014: 1-2 - 2013
- [c1]Benwei Xu, Yun Chiu:
Background calibration of time-interleaved ADC using direct derivative information. ISCAS 2013: 2456-2459
Coauthor Index
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