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Journal Articles
- 2023
[j3]Yibrah Gebreyesus, Damian Dalton, Sebastian Nixon, Davide De Chiara, Marta Chinnici
:
Machine Learning for Data Center Optimizations: Feature Selection Using Shapley Additive exPlanation (SHAP). Future Internet 15(3): 88 (2023)- 2011
- [j2]Christoph Trummer, Christoph Ruggenthaler, Christoph M. Kirchsteiger, Christian Steger, Reinhold Weiß, Markus Pistauer, Damian Dalton:
Searching Extended IP-XACT Components for SoC Design Based on Requirements Similarity. IEEE Syst. J. 5(1): 70-79 (2011) - 2010
- [j1]Christoph Ruggenthaler, Christoph Trummer, Christian Steger, Reinhold Weiß, Andreas Schuhai, Markus Pistauer, Damian Dalton:
An IP-XACT Library extended with verification information for functionality-based component selection. Elektrotech. Informationstechnik 127(4): 109-113 (2010)
Conference and Workshop Papers
- 2010
- [c11]Christoph Trummer, Christoph M. Kirchsteiger, Christian Steger, Reinhold Weiss, Markus Pistauer, Damian Dalton:
Automated simulation-based verification of power requirements for Systems-on-Chips. DDECS 2010: 8-11 - 2005
- [c10]Mario Polaschegg, Christian Steger, Damian Dalton, Abhay Vadher:
Parallel Simulation with a Generic Simulation Framework Featuring Loose Coupling. ICPP Workshops 2005: 251-257 - [c9]Alexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton:
Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator. ISVLSI 2005: 290-291 - 2004
- [c8]Mario Polaschegg, Christian Steger, Damian Dalton, Abhay Vadher:
A Generic Simulation Framework for Multiprocessor Architectures. FDL 2004: 345-355 - [c7]Alexander Maili, Damian Dalton, Christian Steger:
A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment. PATMOS 2004: 799-808 - 2003
- [c6]Damian Dalton, Vivian Bessler, Jeffrey Griffiths, Andrew McCarthy, Abhay Vadher, Rory O'Kane, Rob Quigley, Declan O'Connor:
APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator. FPL 2003: 1162-1165 - 1999
- [c5]Damian Dalton:
Avoiding Conventional Overheads in Parallel Logic Simulation: A New Architecture. HiPC 1999: 364-370 - [c4]Damian Dalton:
Analysis of an Associative Array Parallel Logic Simulator. ICPP Workshops 1999: 308-312 - [c3]Damian Dalton:
The Speedup Performance of an Associative Memory Based Logic Simulator. PaCT 1999: 207-216 - [c2]Damian Dalton:
A special purpose hybrid SIMD processor for logic event simulation. PDP 1999: 74-83 - [c1]Damian Dalton:
A New Timing Mechanism Architecture for Discrete Logic Event Simulation. PDPTA 1999: 1236-1242
Coauthor Index
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