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Books and Theses
- 2007
[b2]Justin Davis, Robert B. Reese:
Finite State Machine Datapath Design, Optimization, and Implementation. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2007, ISBN 978-3-031-79775-0- 2006
- [b1]Robert B. Reese, Mitchell A. Thornton
:
Introduction to Logic Synthesis using Verilog HDL. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2006, ISBN 978-3-031-79742-2
Journal Articles
- 2015
- [j5]Susan Conry, Eric Durant, Herman Lam, Victor P. Nelson, Robert B. Reese:
CE2016 steering committee: a short update. Inroads 6(1): 62 (2015) - 2005
- [j4]Robert B. Reese, Mitchell A. Thornton, Cherrice Traver:
A Coarse-Grain Phased Logic CPU. IEEE Trans. Computers 54(7): 788-799 (2005) - [j3]Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger:
Early evaluation for performance enhancement in phased logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 532-550 (2005) - 2004
- [j2]Jerry W. Bruce, James C. Harden, Robert B. Reese:
Cooperative and progressive design experience for embedded systems. IEEE Trans. Educ. 47(1): 83-92 (2004) - 1997
- [j1]J. Scott Calhoun, Vijay K. Madisetti, Robert B. Reese, Thomas Egolf:
Developing and Distributing Component-Level VHDL Models. J. VLSI Signal Process. 15(1-2): 111-126 (1997)
Conference and Workshop Papers
- 2015
- [c12]Eric Durant, John Impagliazzo, Susan Conry, Robert B. Reese, Herman Lam, Victor P. Nelson, Joseph L. Hughes, Weidong Liu, Junlin Lu, Andrew D. McGettrick:
CE2016: Updated computer engineering curriculum guidelines. FIE 2015: 1-2 - 2014
- [c11]Eric Durant, John Impagliazzo, Susan Conry, Robert B. Reese, Mitchell A. Thornton, Herman Lam, Victor P. Nelson:
Setting the stage for CE2016: A revised body of knowledge. FIE 2014: 1-4 - 2012
- [c10]Robert B. Reese, Scott C. Smith, Mitchell A. Thornton:
Uncle - An RTL Approach to Asynchronous Design. ASYNC 2012: 65-72 - 2004
- [c9]Kenneth Fazel, Lun Li, Mitchell A. Thornton, Robert B. Reese, Cherrice Traver:
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion. ACM Great Lakes Symposium on VLSI 2004: 413-416 - 2003
- [c8]Robert B. Reese, Mitchell A. Thornton, Cherrice Traver:
A Coarse-Grain Phased Logic CPU. ASYNC 2003: 2-13 - [c7]Kenneth Fazel, Mitchell A. Thornton, Robert B. Reese:
PLFire: A Visualization Tool for Asynchronous Phased Logic Designs. DATE 2003: 11096-11097 - [c6]Robert B. Reese, Mitchell A. Thornton, Cherrice Traver:
A Fine-Grain Phased Logic CPU. ISVLSI 2003: 70-79 - 2002
- [c5]Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver:
Generalized Early Evaluation in Self-Timed Circuits. DATE 2002: 255-259 - 2001
- [c4]Robert B. Reese, Mitchell A. Thornton, Cherrice Traver:
Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation. ICCD 2001: 18-23 - 2000
- [c3]Hemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha P. Chandrakasan:
OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet. ICCD 2000: 567-570 - 1999
- [c2]Hemang Lavana, Franc Brglez, Robert B. Reese:
User-configurable experimental design flows on the web: the ISCAS'99 experiments. ISCAS (6) 1999: 440-443 - 1993
- [c1]Richard Auletta, Robert B. Reese, Cherrice Traver:
A Comparison of Synchronous and Asynchronous FSMD Designs. ICCD 1993: 178-182
Coauthor Index
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