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2010 – 2019
- 2011
[j7]Marco Zanuso, Salvatore Levantino
, Carlo Samori, Andrea L. Lacaita:
A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation. IEEE J. Solid State Circuits 46(3): 627-638 (2011)- [j6]Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power. IEEE J. Solid State Circuits 46(12): 2745-2758 (2011) - [j5]Davide Tasca, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL. IEEE Trans. Circuits Syst. II Express Briefs 58-II(4): 200-204 (2011) - [c7]Carlo Samori, Marco Zanuso, Salvatore Levantino, Andrea L. Lacaita:
Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs. ISCAS 2011: 418-421 - [c6]Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power. ISSCC 2011: 88-90 - 2010
- [j4]Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita:
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic. EURASIP J. Embed. Syst. 2010 (2010) - [j3]Marco Zanuso, Paolo Madoglio, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(3): 548-555 (2010) - [c5]Marco Zanuso, Salvatore Levantino, Alberto Puggelli, Carlo Samori, Andrea L. Lacaita:
Time-to-digital converter with 3-ps resolution and digital linearization algorithm. ESSCIRC 2010: 262-265 - [c4]Salvatore Levantino, Marco Zanuso, Carlo Samori, Andrea L. Lacaita:
Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band. ISSCC 2010: 50-51 - [c3]Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation. ISSCC 2010: 476-477
2000 – 2009
- 2009
- [j2]Marco Zanuso, Davide Tasca, Salvatore Levantino, Andrea Donadel, Carlo Samori, Andrea L. Lacaita:
Noise Analysis and Minimization in Bang-Bang Digital PLLs. IEEE Trans. Circuits Syst. II Express Briefs 56-II(11): 835-839 (2009) - [c2]Marco Zanuso, Salvatore Levantino, Davide Tasca, Daniele Raiteri, Carlo Samori, Andrea L. Lacaita:
A glitch-corrector circuit for low-spur ADPLLs. ICECS 2009: 595-598 - [c1]Salvatore Levantino, Marco Zanuso, Davide Tasca, Carlo Samori, Andrea L. Lacaita:
An all-digital architecture for low-jitter regulated delay lines. ICECS 2009: 603-606 - 2007
- [j1]Paolo Madoglio, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
Quantization Effects in All-Digital Phase-Locked Loops. IEEE Trans. Circuits Syst. II Express Briefs 54-II(12): 1120-1124 (2007)
Coauthor Index
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