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Juraj Povazanec
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2000 – 2009
- 2002
- [c7]Jayasanker Jayabalan, Juraj Povazanec:
Integration of SRAM Redundancy into Production Test. ITC 2002: 187-193 - 2001
- [j3]Jan Butas, Chiu-Sing Choy, Juraj Povazanec, Cheong-Fat Chan:
Asynchronous cross-pipelined multiplier. IEEE J. Solid State Circuits 36(8): 1272-1275 (2001) - [j2]Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan:
A New Control Circuit for Asynchronous Micropipelines. IEEE Trans. Computers 50(9): 992-997 (2001) - [c6]Vinod Nair, Martin Erdmann, Shridhar Mubaraq Mishra, Juraj Povazanec, Amit Shaligram, Chun Feng Hu:
A single chip terminal solution for high-end telephone applications. CICC 2001: 417-420
1990 – 1999
- 1999
- [c5]Juraj Povazanec, Oliver Chiu-sing Choy, Cheong-Fat Chan, Jan Butas, Yeu-qiu Zhang, Jing-Ling Yang, Tin-yan Tang:
Pipelined Dataflow Architecture of a Small Processor. PDPTA 1999: 1217-1223 - 1998
- [c4]Oliver Chiu-sing Choy, Tin-Chak Johnson Pang, Juraj Povazanec, Cheong-Fat Chan:
A Useful Micropipeline Architecture to Implement DSP Algorithms. EUROMICRO 1998: 10212- - [c3]Juraj Povazanec, Chiu-Sing Choy, Cheong-Fat Chan:
Asynchronous logic in bit-serial arithmetic. ICECS 1998: 175-178 - 1997
- [j1]Juraj Povazanec, Vladislav Musil:
Fault and test-process modelling for integrated circuits. J. Syst. Archit. 43(1-5): 123-127 (1997) - 1996
- [c2]Juraj Povazanec, Jirí Kaderka, Vladislav Musil, Petr Simek:
Test-Process Simulation with Neural Network Evaluation. ESM 1996: 712-718 - [c1]Jirí Kaderka, Vladislav Musil, Juraj Povazanec, Petr Simek:
Neural network based system for testing and diagnostics of analogue integrated circuits. ICECS 1996: 1198-1201
Coauthor Index
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