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I-Wei Wu
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Journal Articles
- 2015
- [j4]I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors. J. Inf. Sci. Eng. 31(4): 1431-1453 (2015) - 2014
- [j3]I-Wei Wu, Jean Jyh-Jiun Shann, Wei-Chung Hsu, Chung-Ping Chung:
Extended Instruction Exploration for Multiple-Issue Architectures. ACM Trans. Embed. Comput. Syst. 13(4): 92:1-92:28 (2014) - 2011
- [j2]I-Wei Wu, Chung-Ping Chung, Jean Jyh-Jiun Shann:
Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration. J. Inf. Sci. Eng. 27(5): 1641-1657 (2011) - 2002
- [j1]I-Wei Wu, Wen-Shiung Chen, Ho-En Liao, Fongray Frank Young:
A seamless handoff approach of Mobile IP protocol for mobile wireless data networks. IEEE Trans. Consumer Electron. 48(2): 335-344 (2002)
Conference and Workshop Papers
- 2015
- [c8]I-Chun Liu, I-Wei Wu, Jean Jyh-Jiun Shann:
Instruction Emulation and OS Supports of a Hybrid Binary Translator for x86 Instruction Set Architecture. UIC/ATC/ScalCom 2015: 1070-1077 - 2013
- [c7]Yu-Hsin Tsai, I-Wei Wu, I-Chun Liu, Jean Jyh-Jiun Shann:
Improving performance of JNA by using LLVM JIT compiler. ICIS 2013: 483-488 - 2010
- [c6]Hui-Shan Wang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Reconfigurable custom functional unit generation and exploitation in multiple-issue processors. SASP 2010: 115-118 - 2009
- [c5]Jyh-Shian Wang, I-Wei Wu, Yu-Sheng Chen, Jean Jyh-Jiun Shann, Wei-Chung Hsu:
Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor. CSE (2) 2009: 174-181 - 2008
- [c4]Po-Chun Chang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung:
ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor. DAC 2008: 776-779 - [c3]I-Wei Wu, Zhiyuan Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Instruction Set Extension Exploration in Multiple-Issue Architecture. DATE 2008: 764-769 - 2007
- [c2]I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jean Jyh-Jiun Shann:
Instruction Set Extension Generation with Considering Physical Constraints. HiPEAC 2007: 291-305 - 2006
- [c1]Bin-Hua Tein, I-Wei Wu, Chung-Ping Chung:
Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer. CDES 2006: 91-96
Coauthor Index
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