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ORCIDS. Srinivasan 0001
Person information
- affiliation: IIT Madras
Other persons with the same name
- S. Srinivasan — disambiguation page
- S. Srinivasan 0002 — Texas Southern University (and 2 more)
- S. Srinivasan 0003 — Anna University, Chennai
- S. Srinivasan 0004 — Annamalai University, Department of Mathematics
- S. Srinivasan 0005
![[0000-0002-9066-1907]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-9066-1907")
— St. Peters University, Avadi, Chennai, India
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2010 – 2019
- 2011
[c14]S. Srinivasan, V. Kamakoti, A. Bhattacharya:
Towards Quick Solutions for Generalized Placement Problem. ISED 2011: 106-111- 2010
- [j7]Kavish Seth, V. Kamakoti, S. Srinivasan:
Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation. IEEE Trans. Broadcast. 56(4): 467-480 (2010)
2000 – 2009
- 2007
- [c13]Kannan Gaddam, Nitin Chandrachoodan, S. Srinivasan:
Rapid Abstract Control Model for Signal Processing Implementation. SiPS 2007: 418-423 - 2006
- [j6]P. Rajesh Kumar, K. Sridharan, S. Srinivasan:
A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment. Parallel Comput. 32(3): 205-221 (2006) - [c12]Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti:
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. VLSI Design 2006: 517-520 - 2005
- [j5]Seetharaman Ramachandran, S. Srinivasan:
Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization. J. Syst. Archit. 51(6-7): 435-450 (2005) - 2004
- [c11]Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar:
A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. VLSI Design 2004: 1071-1076 - 2003
- [c10]Seetharaman Ramachandran, S. Srinivasan:
Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization. DSD 2003: 206-213 - [c9]Kumud Prakash Gupta, S. Srinivasan:
Reduced Memory Implementation of Modified Serial Watershed Algorithm Based On Ordered Queue. ITCC 2003: 514-518 - [c8]A. Durga Kishore, S. Srinivasan:
A Distributed Memory Architecture for Morphological Image Processing. ITCC 2003: 536-540 - [c7]Srikar Movva, S. Srinivasan:
A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI. VLSI Design 2003: 202-207 - 2002
- [j4]Seetharaman Ramachandran, S. Srinivasan:
A fast, FPGA-based MPEG-2 video encoder with a novel automatic quality control scheme. Microprocess. Microsystems 25(9-10): 449-457 (2002) - [j3]Seetharaman Ramachandran, S. Srinivasan:
A Novel, Automatic Quality Control Scheme for Real Time Image Transmission. VLSI Design 14(4): 329-335 (2002) - [j2]Seetharaman Ramachandran, S. Srinivasan:
A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse-grain Parallelism. VLSI Design 15(2): 521-528 (2002) - [c6]Kavish Seth, S. Srinivasan:
VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme. ASP-DAC/VLSI Design 2002: 435-440 - 2001
- [c5]Seetharaman Ramachandran, S. Srinivasan:
FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression. FPGA 2001: 213-219 - 2000
- [c4]Seetharaman Ramachandran, S. Srinivasan:
A programmable pruning level control based MPEG video encoder. ISCAS 2000: 571-574 - [c3]Seetharaman Ramachandran, S. Srinivasan:
Design and implementation of an EPLD-based variable length coder for real time image compression applications. ISCAS 2000: 607-610
1990 – 1999
- 1999
- [c2]Seetharaman Ramachandran, S. Srinivasan, R. Chen:
EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression. ISCAS (3) 1999: 375-378 - [c1]D. V. R. Murthy, Seetharaman Ramachandran, S. Srinivasan:
Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs. VLSI Design 1999: 336-339
1980 – 1989
- 1986
- [j1]P. Prabhakar Rao, S. Srinivasan:
New design for an 82720-based colour graphics generator. Microprocess. Microsystems 10(7): 386-391 (1986)
Coauthor Index
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