default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDS. Srinivasan 0001
Person information
- affiliation: IIT Madras
Other persons with the same name
- S. Srinivasan — disambiguation page
- S. Srinivasan 0002 — Texas Southern University (and 2 more)
- S. Srinivasan 0003 — Anna University, Chennai
- S. Srinivasan 0004 — Annamalai University, Department of Mathematics
- S. Srinivasan 0005
![[0000-0002-9066-1907]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-9066-1907")
— St. Peters University, Avadi, Chennai, India
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2010 – 2019
- 2011
[c14]S. Srinivasan, V. Kamakoti, A. Bhattacharya:
Towards Quick Solutions for Generalized Placement Problem. ISED 2011: 106-111- 2010
- [j7]Kavish Seth, V. Kamakoti, S. Srinivasan:
Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation. IEEE Trans. Broadcast. 56(4): 467-480 (2010)
2000 – 2009
- 2007
- [c13]Kannan Gaddam, Nitin Chandrachoodan, S. Srinivasan:
Rapid Abstract Control Model for Signal Processing Implementation. SiPS 2007: 418-423 - 2006
- [j6]P. Rajesh Kumar, K. Sridharan, S. Srinivasan:
A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment. Parallel Comput. 32(3): 205-221 (2006) - [c12]Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti:
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. VLSI Design 2006: 517-520 - 2005
- [j5]Seetharaman Ramachandran, S. Srinivasan:
Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization. J. Syst. Archit. 51(6-7): 435-450 (2005) - 2004
- [c11]Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar:
A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. VLSI Design 2004: 1071-1076 - 2003
- [c10]Seetharaman Ramachandran, S. Srinivasan:
Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization. DSD 2003: 206-213 - [c9]Kumud Prakash Gupta, S. Srinivasan:
Reduced Memory Implementation of Modified Serial Watershed Algorithm Based On Ordered Queue. ITCC 2003: 514-518 - [c8]A. Durga Kishore, S. Srinivasan:
A Distributed Memory Architecture for Morphological Image Processing. ITCC 2003: 536-540 - [c7]Srikar Movva, S. Srinivasan:
A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI. VLSI Design 2003: 202-207 - 2002
- [j4]Seetharaman Ramachandran, S. Srinivasan:
A fast, FPGA-based MPEG-2 video encoder with a novel automatic quality control scheme. Microprocess. Microsystems 25(9-10): 449-457 (2002) - [j3]Seetharaman Ramachandran, S. Srinivasan:
A Novel, Automatic Quality Control Scheme for Real Time Image Transmission. VLSI Design 14(4): 329-335 (2002) - [j2]Seetharaman Ramachandran, S. Srinivasan:
A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse-grain Parallelism. VLSI Design 15(2): 521-528 (2002) - [c6]Kavish Seth, S. Srinivasan:
VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme. ASP-DAC/VLSI Design 2002: 435-440 - 2001
- [c5]Seetharaman Ramachandran, S. Srinivasan:
FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression. FPGA 2001: 213-219 - 2000
- [c4]Seetharaman Ramachandran, S. Srinivasan:
A programmable pruning level control based MPEG video encoder. ISCAS 2000: 571-574 - [c3]Seetharaman Ramachandran, S. Srinivasan:
Design and implementation of an EPLD-based variable length coder for real time image compression applications. ISCAS 2000: 607-610
1990 – 1999
- 1999
- [c2]Seetharaman Ramachandran, S. Srinivasan, R. Chen:
EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression. ISCAS (3) 1999: 375-378 - [c1]D. V. R. Murthy, Seetharaman Ramachandran, S. Srinivasan:
Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs. VLSI Design 1999: 336-339
1980 – 1989
- 1986
- [j1]P. Prabhakar Rao, S. Srinivasan:
New design for an 82720-based colour graphics generator. Microprocess. Microsystems 10(7): 386-391 (1986)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-06-29 00:46 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
