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2010 – 2019
- 2015
[c7]Harish Anil Jamakhandi, Tilak D., Manikantan K., Seetharaman Ramachandran:
Tsallis entropy and particle swarm optimization-based cyclone image vortex localization. ICACCI 2015: 235-244
2000 – 2009
- 2005
- [j4]Seetharaman Ramachandran, S. Srinivasan:
Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization. J. Syst. Archit. 51(6-7): 435-450 (2005) - 2003
- [c6]Seetharaman Ramachandran, S. Srinivasan:
Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization. DSD 2003: 206-213 - 2002
- [j3]Seetharaman Ramachandran, S. Srinivasan:
A fast, FPGA-based MPEG-2 video encoder with a novel automatic quality control scheme. Microprocess. Microsystems 25(9-10): 449-457 (2002) - [j2]Seetharaman Ramachandran, S. Srinivasan:
A Novel, Automatic Quality Control Scheme for Real Time Image Transmission. VLSI Design 14(4): 329-335 (2002) - [j1]Seetharaman Ramachandran, S. Srinivasan:
A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse-grain Parallelism. VLSI Design 15(2): 521-528 (2002) - 2001
- [c5]Seetharaman Ramachandran, S. Srinivasan:
FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression. FPGA 2001: 213-219 - 2000
- [c4]Seetharaman Ramachandran, S. Srinivasan:
A programmable pruning level control based MPEG video encoder. ISCAS 2000: 571-574 - [c3]Seetharaman Ramachandran, S. Srinivasan:
Design and implementation of an EPLD-based variable length coder for real time image compression applications. ISCAS 2000: 607-610
1990 – 1999
- 1999
- [c2]Seetharaman Ramachandran, S. Srinivasan, R. Chen:
EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression. ISCAS (3) 1999: 375-378 - [c1]D. V. R. Murthy, Seetharaman Ramachandran, S. Srinivasan:
Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs. VLSI Design 1999: 336-339
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