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2020 – today
- 2023
[c11]Chuin-Mu Wang, Shao Wei Chu, Yen-Ching Wu, Jia-Xian Jian, Ming-Yu Tsai, Meng-Fen Huang:
Image Recognition Technology for Abnormal Capsule Detection. BCD 2023: 378-381
2010 – 2019
- 2015
- [c10]Ming-Yu Tsai, Yaw-Chung Chen:
A Virtual Cluster Head Election Scheme for Energy-Efficient Routing in Wireless Sensor Networks. FiCloud 2015: 341-348 - 2010
- [j5]Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen:
Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment. IEEE Trans. Circuits Syst. II Express Briefs 57-II(1): 21-25 (2010) - [j4]Tso-Bing Juang, Chin-Chieh Chiu, Ming-Yu Tsai:
Improved Area-Efficient Weighted Modulo 2n + 1 Adder Design With Simple Correction Schemes. IEEE Trans. Circuits Syst. II Express Briefs 57-II(3): 198-202 (2010)
2000 – 2009
- 2009
- [j3]Tso-Bing Juang, Ming-Yu Tsai, Chin-Chieh Chiu:
Corrections to "VLSI Design of Diminished-One Modulo 2n + 1 Adder Using Circular Carry Selection" [Sep 08 897-901]. IEEE Trans. Circuits Syst. II Express Briefs 56-II(3): 260-261 (2009) - 2008
- [c9]Shen-Fu Hsiao, Hsin-Mau Lee, Yen-Chun Cheng, Ming-Yu Tsai:
Efficient designs of flaoting-point CORDIC rotation and vectoring operations. APCCAS 2008: 1422-1425 - [c8]Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen:
Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. ISCAS 2008: 2022-2025 - 2006
- [c7]Shen-Fu Hsiao, Sze-Yun Lin, Tze-Chong Cheng, Ming-Yu Tsai:
An Automatic Cache Generator Based on Content-Addressable Memory. APCCAS 2006: 1313-1316 - [c6]Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen:
Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. APCCAS 2006: 1631-1634 - [c5]Shen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, Tze-Chong Cheng:
Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding. MTDT 2006: 34-42 - 2005
- [j2]Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai, Jenq-Shiun Jan:
A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition. IEICE Trans. Inf. Syst. 88-D(7): 1464-1471 (2005) - [c4]Ming-Yu Tsai, Li-Chen Fu, Ta-Chiun Chou:
Automatic Negotiation with Mediated Agents in E-commerce Marketplace. EEE 2005: 50-53 - [c3]Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen:
An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. ISCAS (3) 2005: 2433-2436 - 2004
- [j1]Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai:
Para-CORDIC: parallel CORDIC rotation algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(8): 1515-1524 (2004) - [c2]Shun-Fa Chang, Li-Chen Fu, Ming-Yu Tsai:
Automatic Integration of Inter-Enterprise Processes with Hierarchical Broker Framework. ICEIS (4) 2004: 62-69 - 2002
- [c1]Tso-Bing Juang, Jeng-Hsiun Jan, Ming-Yu Tsai, Shen-Fu Hsiao:
Partition methodology for the final adder in a tree-structure parallel multiplier generator. APCCAS (1) 2002: 471-474
Coauthor Index
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