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ORCIDSupamas Sirichotiyakul
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Journal Articles
- 2003
[j3]Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul:
Probabilistic analysis of interconnect coupling noise. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9): 1188-1203 (2003)- [j2]David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh:
Driver modeling and alignment for worst-case delay noise. IEEE Trans. Very Large Scale Integr. Syst. 11(2): 157-166 (2003) - 2002
- [j1]Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David T. Blaauw:
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 79-90 (2002)
Conference and Workshop Papers
- 2002
- [c8]Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul:
Estimation of the likelihood of capacitive coupling noise. DAC 2002: 653-658 - [c7]Vladimir Zolotov, David T. Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy:
Noise propagation and failure criteria for VLSI designs. ICCAD 2002: 587-594 - 2001
- [c6]Supamas Sirichotiyakul, David T. Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo:
Driver Modeling and Alignment for Worst-Case Delay Noise. DAC 2001: 720-725 - [c5]Alexey Glebov, Sergey Gavrilov
, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov:
False-Noise Analysis using Logic Implications. ICCAD 2001: 515- - [c4]Murat R. Becer, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj:
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. ISQED 2001: 158-163 - 2000
- [c3]Rafi Levy, David T. Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov:
ClariNet: a noise analysis tool for deep submicron design. DAC 2000: 233-238 - 1999
- [c2]Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw:
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC 1999: 436-441 - 1998
- [c1]David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards:
Emerging power management tools for processor design. ISLPED 1998: 143-148
Coauthor Index
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