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ORCIDDennis Michael Fischette
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2010 – 2019
- 2014
[c6]William Walker, Dennis Michael Fischette:
Wireline clocking and equalization. CICC 2014: 1- 2013
- [c5]Dennis Michael Fischette, Jaeha Kim:
Wireline transmitter and receiver design techniques. CICC 2013: 1 - 2012
- [j2]Alvin Leng Sun Loke, Bruce Andrew Doyle, Sanjeev K. Maheshwari, Dennis Michael Fischette, Charles Lin Wang, Tin Tin Wee, Emerson S. Fang:
An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors. IEEE J. Solid State Circuits 47(11): 2627-2642 (2012) - 2011
- [c4]Bruce Andrew Doyle, Alvin Leng Sun Loke, Sanjeev K. Maheshwari, Charles Lin Wang, Dennis Michael Fischette, Jeffrey G. Cooper, Sanjeev K. Aggarwal, Tin Tin Wee, Chad O. Lackey, Harishkumar S. Kedarnath, Michael M. Oshima, Gerry R. Talbot, Emerson S. Fang:
Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors. A-SSCC 2011: 133-136 - 2010
- [j1]Dennis Michael Fischette, Alvin Leng Sun Loke, Richard Joseph DeSantis, Gerry R. Talbot:
An Embedded All-Digital Circuit to Measure PLL Response. IEEE J. Solid State Circuits 45(8): 1492-1503 (2010) - [c3]Dennis Michael Fischette, Alvin Leng Sun Loke, Michael M. Oshima, Bruce Andrew Doyle, Roland Bakalski, Richard Joseph DeSantis, Anand Thiruvengadam, Charles Lin Wang, Gerry R. Talbot, Emerson S. Fang:
A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O. ISSCC 2010: 246-247
2000 – 2009
- 2009
- [c2]Dennis Michael Fischette, Richard Joseph DeSantis, John H. Lee:
An on-chip all-digital measurement circuit to characterize phase-locked loop response in 45-nm SOI. CICC 2009: 609-612 - 2008
- [c1]Dennis Michael Fischette, Kimo Tam:
Session 17 - Clocking circuits. CICC 2008
Coauthor Index
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