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ORCIDJuan A. López
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Journal Articles
- 2014
[j6]Pablo Barrio, Carlos Carreras
, Juan A. López, Óscar Robles, Ruzica Jevtic, Roberto Sierra:
Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes. J. Syst. Archit. 60(7): 579-591 (2014)- 2012
- [j5]Gabriel Caffarena, Olivier Sentieys, Daniel Ménard, Juan A. López, David Novo:
Quantization of VLSI digital signal processing systems. EURASIP J. Adv. Signal Process. 2012: 32 (2012) - 2010
- [j4]Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero:
SQNR Estimation of Fixed-Point DSP Algorithms. EURASIP J. Adv. Signal Process. 2010 (2010) - 2009
- [j3]Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz:
Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs. Int. J. Reconfigurable Comput. 2009: 703267:1-703267:14 (2009) - 2008
- [j2]Juan A. López, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz:
Fast and accurate computation of the roundoff noise of linear time-invariant systems. IET Circuits Devices Syst. 2(4): 393-408 (2008) - 2007
- [j1]Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz:
Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 1923-1933 (2007)
Conference and Workshop Papers
- 2023
- [c13]Ignacio Amat Hernández, Juan A. López:
Any-Radix Efficient Fully-Parallel Implementation of the Fast Fourier Transform on FPGAs. DCIS 2023: 1-6 - 2020
- [c12]Luis Esteban, Juan Antonio López Martín, Alberto Regadío:
Round-off noise estimation of fixed-point algorithms using Modified Affine Arithmetic and Legendre Polynomials. DCIS 2020: 1-6 - 2014
- [c11]Enrique Sedano, Daniel Ménard, Juan A. López:
Automated Data Flow Graph Partitioning for a Hierarchical Approach to Wordlength Optimization. ARC 2014: 133-143 - 2010
- [c10]Gabriel Caffarena, Juan A. López, Angel Fernandez Herrero, Carlos Carreras:
SQNR estimation of non-linear fixed-point algorithms. EUSIPCO 2010: 522-526 - [c9]Gabriel Caffarena, Angel Fernandez Herrero, Juan A. López, Carlos Carreras:
Fast Fixed-Point Optimization of DSP Algorithms. VLSI-SoC (Selected Papers) 2010: 182-205 - [c8]Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero:
Fast fixed-point optimization of DSP algorithms. VLSI-SoC 2010: 195-200 - 2008
- [c7]Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz:
Optimized Architectural Synthesis of Fixed-Point Datapaths. ReConFig 2008: 85-90 - 2006
- [c6]Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz:
High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. FPL 2006: 1-4 - [c5]Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz:
Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources. SoC 2006: 1-4 - 2004
- [c4]Juan A. López, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz:
Analysis of limit cycles by means of affine arithmetic computer-aided tests. EUSIPCO 2004: 991-994 - [c3]Gabriel Caffarena, Slobodan Bojanic, Juan A. López, Carlos E. Pedreira, Octavio Nieto-Taladriz:
High-speed systolic array for gene matching. FPGA 2004: 248 - 2003
- [c2]Juan A. López, Carlos Carreras, Gabriel Caffarena, Octavio Nieto-Taladriz:
Fast characterization of the noise bounds derived from coefficient and signal quantization. ISCAS (4) 2003: 309-312 - 1999
- [c1]Carlos Carreras, Juan A. López, Octavio Nieto-Taladriz:
Bit-Width Selection for Data-Path Implementations. ISSS 1999: 114-121
Coauthor Index
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