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ORCIDNai-Chen Cheng 0001
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- affiliation: Industrial Technology Research Institute (ITRI), Information and Communications Research Lab, Hsinchu, Taiwan
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2020 – today
- 2024
[c8]Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Tze-Chiang Huang, Wen-Hung Huang, Kate Huang, Yu-Chi Chen, Alex Liu, Yu-Jie Huang, Jimmy Wang, Shu-Chun Yang, Nai-Chen Cheng, Chao-Chieh Li, Hsin-Hung Kuo, Wei-Chih Chen, Chin-Hua Wen, Kevin Lin, Po-Yi Huang, Kenny Cheng-Hsiang Hsieh, Frank Lee:
A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4. VLSI Technology and Circuits 2024: 1-2
2010 – 2019
- 2016
- [c7]Ting-Chou Lu, Li-Ren Huang, Yu Lee, Kun-Ju Tsai, Yu-Te Liao
, Nai-Chen Cheng, Yuan-Hua Chu, Yi-Hsing Tsai, Fang-Chu Chen, Tzi-cker Chiueh:
Invited - Wireless sensor nodes for environmental monitoring in internet of things. DAC 2016: 3:1-3:5 - [c6]Shu-Hsuan Lin, Fu-To Lin, Nai-Chen Cheng, Yu-Te Liao:
A 0.8V, 43.5μW ECG signal acquisition IC with a referenceless time-to-digital converter. ISCAS 2016: 1066-1069 - 2013
- [c5]Chih-Hsiang Chang, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng, Nai-Chen Cheng:
A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS. ESSCIRC 2013: 53-56 - [c4]Yu-Lin Tsou, Nai-Chen Daniel Cheng, Christina F. Jou:
A 32.4 μW RF front end for 2.4 GHz wake-up receiver. ISCAS 2013: 125-128 - 2010
- [c3]Yu Lee, Ching-Yuan Yang, Nai-Chen Daniel Cheng, Ji-Jan Chen:
An embedded wide-range and high-resolution CLOCK jitter measurement circuit. DATE 2010: 1637-1640
2000 – 2009
- 2008
- [c2]Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen:
Experimental Results of Built-In Jitter Measurement for Gigahertz Clock. ATS 2008: 268 - 2007
- [c1]Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen:
A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement. ATS 2007: 219-223
Coauthor Index
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