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ORCIDSeongil O
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- affiliation: Seoul National University, South Korea
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2020 – today
- 2022
[c12]Dae-Hyun Kim
, Byungkyu Song, Hyun-A. Ahn, Woongjoon Ko, Sung-Geun Do, Seokjin Cho, Kihan Kim, Seung-Hoon Oh, Hye-Yoon Joo, Geuntae Park, Jin-Hun Jang, Yong-Hun Kim, Donghun Lee, Jaehoon Jung, Yongmin Kwon, Youngjae Kim, Jaewoo Jung, Seongil O, Seoulmin Lee, Jaeseong Lim, Junho Son, Jisu Min, Haebin Do, Jaejun Yoon, Isak Hwang, Jinsol Park, Hong Shim, Seryeong Yoon, Dongyeong Choi, Jihoon Lee, Soohan Woo, Eunki Hong, Junha Choi, Jae-Sung Kim, Sangkeun Han, Jong-Min Bang, Bokgue Park, Jang-Hoo Kim, Seouk-Kyu Choi, Gong-Heum Han, Yoo-Chang Sung, Wonil Bae, Jeong-Don Lim, Seungjae Lee, Changsik Yoo, Sang Joon Hwang, Jooyoung Lee:
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process. ISSCC 2022: 448-450- 2021
- [c11]Suk Han Lee, Shinhaeng Kang, Jaehoon Lee, Hyeonsu Kim, Eojin Lee, Seungwoo Seo, Hosang Yoon, Seungwon Lee, Kyounghwan Lim, Hyunsung Shin, Jinhyun Kim, Seongil O, Anand Iyer, David Wang, Kyomin Sohn, Nam Sung Kim:
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product. ISCA 2021: 43-56 - [c10]Young-Cheon Kwon, Suk Han Lee, Jaehoon Lee, Sang-Hyuk Kwon, Je-Min Ryu, Jong-Pil Son, Seongil O, Hak-soo Yu, Haesuk Lee, Soo Young Kim, Youngmin Cho, Jin Guk Kim, Jongyoon Choi, Hyunsung Shin, Jin Kim, BengSeng Phuah, Hyoungmin Kim, Myeong Jun Song, Ahn Choi, Daeho Kim, Sooyoung Kim, Eun-Bong Kim, David Wang, Shinhaeng Kang, Yuhwan Ro, Seungwoo Seo, Joon-Ho Song, Jaeyoun Youn, Kyomin Sohn, Nam Sung Kim:
25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications. ISSCC 2021: 350-352
2010 – 2019
- 2018
- [c9]Sukhan Lee, Kiwon Lee, Min Chul Sung, Mohammad Alian, Chankyung Kim, Wooyeong Cho, Reum Oh, Seongil O, Jung Ho Ahn, Nam Sung Kim:
3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions. PACT 2018: 22:1-22:12 - 2017
- [c8]Sang-uhn Cha, Seongil O, Hyunsung Shin, Sangjoon Hwang, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Gyo-Young Jin, Young Hoon Son, Hyunyoon Cho, Jung Ho Ahn, Nam Sung Kim:
Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices. HPCA 2017: 61-72 - 2016
- [j3]Sheng Li, Hyeontaek Lim, Victor W. Lee, Jung Ho Ahn, Anuj Kalia, Michael Kaminsky, David G. Andersen, Seongil O, Sukhan Lee, Pradeep Dubey:
Achieving One Billion Key-Value Requests per Second on a Single Server. IEEE Micro 36(3): 94-104 (2016) - [j2]Sheng Li, Hyeontaek Lim, Victor W. Lee, Jung Ho Ahn, Anuj Kalia, Michael Kaminsky, David G. Andersen, Seongil O, Sukhan Lee, Pradeep Dubey:
Full-Stack Architecting to Achieve a Billion-Requests-Per-Second Throughput on a Single Key-Value Store Server Platform. ACM Trans. Comput. Syst. 34(2): 5:1-5:30 (2016) - 2015
- [j1]Seongil O, Sanghyuk Kwon, Young Hoon Son, Yujin Park, Jung Ho Ahn:
CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults. IEEE Comput. Archit. Lett. 14(1): 17-20 (2015) - [c7]Young Hoon Son, Sukhan Lee, Seongil O, Sanghyuk Kwon, Nam Sung Kim, Jung Ho Ahn:
CiDRA: A cache-inspired DRAM resilience architecture. HPCA 2015: 502-513 - [c6]Ke Chen, Sheng Li, Jung Ho Ahn, Naveen Muralimanohar, Jishen Zhao, Cong Xu, Seongil O, Yuan Xie, Jay B. Brockman, Norman P. Jouppi:
History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. ICS 2015: 251-261 - [c5]Sheng Li, Hyeontaek Lim, Victor W. Lee, Jung Ho Ahn, Anuj Kalia, Michael Kaminsky, David G. Andersen, Seongil O, Sukhan Lee, Pradeep Dubey:
Architecting to achieve a billion requests per second throughput on a single key-value store server platform. ISCA 2015: 476-488 - 2014
- [c4]Seongil O, Young Hoon Son, Nam Sung Kim, Jung Ho Ahn:
Row-buffer decoupling: A case for low-latency DRAM microarchitecture. ISCA 2014: 337-348 - [c3]Young Hoon Son, Seongil O, Hyunggyun Yang, Daejin Jung, Jung Ho Ahn, John Kim, Jangwoo Kim, Jae W. Lee:
Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems. SC 2014: 1059-1070 - 2013
- [c2]Young Hoon Son, Seongil O, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn:
Reducing memory access latency with asymmetric DRAM bank organizations. ISCA 2013: 380-391 - [c1]Jung Ho Ahn, Sheng Li, Seongil O, Norman P. Jouppi:
McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling. ISPASS 2013: 74-85
Coauthor Index
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