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ORCIDMicroprocessors and Microsystems, Volume 19
Volume 19, Number 1, 1995
- J. R. Elphick, Tim Clarke
, S. T. Lawes:
A high-performance analogue input/output system for transputer applications. 3-8 - Peter K. Sharpe, Alan Chalmers, Dominic A. P. Greenwood:
Genetic algorithms for generating minimum path configurations. 9-14 - Ian Andrew Grout, S. E. Burge, A. P. Dorey:
Design and testing of a PI controller ASIC. 15-22 - Fei Xia, Sergio A. Velastin, Anthony C. Davies:
Evaluation of the Data Interaction Architecture Demonstrator by means of a multiple mobile robot workspace simulation. 23-33 - Jeffrey S. Snyder, David B. Whalley, Theodore P. Baker:
Fast context switches: compiler and architectural support for preemptive scheduling. 35-42 - Constantinos V. Papadopoulos, Theodoros Andronikos:
Modelling the complexity of parallel and VLSI computations with Boolean circuits. 43-50 - M. H. Cheung, K. M. Shea, Francis C. M. Lau:
A technique for process pre-emption in the transputer. 51-56 - R. Nagarajan, Tan Le Lay, Goh Mei Lin:
A static fault detection system for digital integrated circuits. 57-63
Volume 19, Number 2, 1995
- Gordon Belcher:
Differences between civil and military electronic flight control systems. 67-74 - Dominique Brière, Christian Favre, Pascal Traverse:
A family of fault-tolerant systems: electrical flight controls, from Airbus A320/330/340 to future military transport aircraft. 75-82 - B. Bauer, C. Bouvier:
Real-time Ada applications with silicon executives. 83-88 - W. Straube:
EFA modular computer concept. 89-94 - K. P. Dawson, A. J. Lee:
Performance engineering - how well does it really work? 95-99 - Michael A. Hennell, J. Alan Prudom:
A dual viewpoint software test tool. 101-104 - António de Brito Ferrari:
Sparc® architecture, assembly language programming, & C : Richard P Paul Prentice-Hall Inc, Englewood Cliffs, NJ, USA (1994) ISBN 0 13 876889 7, £34.75, 448 pp. 105-106 - Brian Dickinson:
VHDL '92: The new features of the VHDL hardware description language : Jean-Michel Bergé, Alain Fonkoua, Serge Maginot and Jacques Rouillard Kluwer Academic Publishers, Dortrecht, The Netherlands (1993) ISBN 0 7923 9356 2, Dfl 180.00, £65.50, pp214. 106-107 - Chris R. Jesshope:
Multiprocessing: Trade-offs in computation and communication : Vijay K Naik Kluwer Academic Publishers, Dordrecht, The Netherlands (1993) ISBN 0 7923 9370 8, Dfl 180.00, £65.50, pp224. 107
Volume 19, Number 3, 1995
- John N. Lygouras, A. Kapsopoulos, Philippos G. Tsalides:
High speed RS-232 fibre optic communication system for underwater remotely operated vehicles. 115-120 - Douglas W. Miller, David T. Harper III:
Performance analysis of disk cache write policies. 121-130 - C. P. Ravikumar, Rajender Sethi:
SHARP: A shape recognition system and its parallel implementation. 131-138 - Sadiq M. Sait, Muhammad A. A. Khalid:
VLSI design and implementation of systolic tree queues. 139-146 - Fatih Kurugöllü, Hasan Palaz, Halûk Gümüskaya, A. Emre Harmanci, Bülent Örencik:
Advanced educational parallel DSP system based on TMS320C25 processors. 147-156 - Patrick Lidstone, Michael Horwood, Jim Baker:
A dynamically reconfigurable parallel processing system. 157-160 - Rana Ejaz Ahmed:
Cascade signature and syndrome compression. 161-163 - NiMH and NiCd battery management. 165-174
Volume 19, Number 4, 1995
- James E. L. Hollis, T. E. Cronk:
Transputer implementation of interpolators for radar image transformations. 179-183 - Z. Hu, G. A. King:
A bit-level systolic implementation of the median filter. 185-186 - Steven Wallace, Nader Bagherzadeh:
Performance issues of a superscalar microprocessor. 187-199 - Ernesto F. V. Martins, António Nunes da Cruz:
A self-selection distributed arbiter for a multiprocessor. 201-207 - Rabin Deka:
A comprehensive study of digital signal processing devices. 209-221 - Mehmet B. Akhan, Ömer A. Yedekçioglu:
A RISC based protocol converter for IBM mainframes. 223-229 - Himanshu S. Mazumdar:
A multilayered feed forward neural network suitable for VLSI implementation. 231-234 - I. M. Parker:
High speed memory organization. 235-236
Volume 19, Number 5, 1995
- Colin D. Walter:
Verification of hardware combining multiplication, division and square root. 243-245 - Ioannis Andreadis, K. Stavroglou, Philippos Tsalides:
Design and VLSI implementation of an ASIC for real-time manipulation of digital colour images. 247-253 - B. H. Tan, E. Tan, K. T. Lau, S. C. Mar:
Design and implementation of an FPGA transponder. 255-259 - Simon R. Wiseman, Hugh S. Field-Richards:
Holistic computing. 261-267 - Wai Lung Loh:
BEE: a special-purpose machine for hardware description languages. 269-276 - Wei-Wei Lu, Michael Paul Gough:
Adaptive cosine transform coding for compression of Mars-96 ELISMA instrument data. 277-282 - Christopher J. Turner, Virendrakumar C. Bhavsar, Przemyslaw Pochec:
Parallel implementations of convolution and moments algorithms on a multi-transputer system. 283-290 - M. Osman Tokhi, M. Alamgir Hossain:
CISC, RISC and DSP processors in real-time signal processing and control. 291-300
Volume 19, Number 6, August 1995
- Muhammad K. Dhodhi, Imtiaz Ahmad, Robert H. Storer:
SHEMUS: synthesis of heterogeneous multiprocessor systems. 311-319 - Marco Chirico, Ermanno Di Zitti, Giacomo M. Bisio:
A linear rotation based solution of large systems on a transputer array. 321-326 - S. Raman, E. R. Shaji:
ASIC design of a matching unit for NLP. 327-340 - Kemal Efe:
Statistical analysis of parallel randomized algorithms for VLSI placement and implementation on workstation networks. 341-349 - Allan M. Macleod, Peter F. Martin, W. Allan Gillespie:
Development of a real-time, 20 mega-samples per second, 32 channel data acquisition system. 351-359 - Alessandro Gandelli, Vincenzo Piuri:
Design and implementation of a massively parallel architecture for high-level electronic measurements. 361-373
Volume 19, Number 7, September 1995
- V. Lakshmi Narasimhan, S. Price-White:
Design and implementation of a scalable low-cost shared-memory multiprocessor system using IBM compatible PCs. 383-394 - Thambipillai Srikanthan, Kai-Yun Chan, Hock Soon Seah, S. K. Leong:
A transputer based vehicle simulator. 395-404 - Piers A. Shallow:
Parallelization of the stack. 405-411 - Alberto Bartoli, Gianluca Dini:
Implementing distributed process farms. 413-422 - William A. Gowan:
Optical character recognition using fuzzy logic. 423-434
Volume 19, Number 8, October 1995
- Timo Hämäläinen, Jukka Saarinen, Kimmo Kaski:
TUTNC: a general purpose parallel computer for neural network computations. 447-465 - Imtiaz Ahmad, Muhammad K. Dhodhi, Kassem Saleh:
An evolutionary technique for local microcode compaction. 467-474 - Larry Hughes, Glenn Stoddart:
Fault-tolerant process tracking in Lego. 475-479 - Brian Dipert, Ken McKee:
Performance benefits and power/energy savings of 28FOl6XS-based system designs. 481-487
Volume 19, Number 9, 1995
- James M. Kirby:
System development - the challenges of re-useability. 503-510 - Dominique Brière, D. Ribot, Daniel Pilaud, J.-L. Camus:
Method and specification tools for Airbus onboard systems. 511-515 - A. D. Hutcheon, D. T. Jordan, John A. McDermid, R. H. Pierce, I. C. Wand, B. J. Jepson:
High integrity software development: process and tool issues. 517-524 - Kostas N. Tarchanidis, A. S. Mackay, J. Lucas:
Flexible kinematics for modular robots. 525-532 - Richard P. Halverson Jr., Art Lew:
FPGAs for expression level parallel processing. 533-540 - David N. J. White:
Interfacing Inmos links to the ISA bus. 541-551
Volume 19, Number 10, December 1995
- H. H. Hesselink:
A comparison of standards for software engineering based on DO-178B for certification of avionics systems. 559-563 - A. Kröger:
Data flow oriented control law design with the graphical language HOSTESS. 565-574 - A. Cook:
ARINC 653 - Challenges of the present and future. 575-579 - King-Jet Tseng:
DSP-based control of brushless DC drives for direct-driven robotic arms. 581-589 - Peter K. K. Loh:
Heuristic fault-tolerant routing strategies for a multiprocessor network. 591-597 - Gab Seon Rho, Kyeonghoon Koo, Naehyuck Chang, Jaehyun Park, Yeong-gi Kim, Wook Hyun Kwon:
Implementation of a RISC microprocessor for programmable logic controllers. 599-608 - Savo Savic, Milo Tomasevic, Veljko Milutinovic, Anil Gupta, Mark Natale, Ilya Gertner:
Improved RMS for the PC environment. 609-619
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