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ORCIDIET Computers & Digital Techniques, Volume 7
Volume 7, Number 1, January 2013
- David S. Broomhead, Steve B. Furber
, Marianne Johnson:
Algebraic approach to time borrowing. 1-10 - Cheoljon Jang, Jaehwan Kim, Byung-Gyu Ahn, Jongwha Chong:
Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits. 11-20 - Irith Pomeranz:
Static test compaction for mixed broadside and skewed-load transition fault test sets. 21-28 - George Athanasiou, Harris E. Michail, George Theodoridis, Costas E. Goutis:
High-performance FPGA implementations of the cryptographic hash function JH. 29-40 - Takahiro Sasaki, Tomoyuki Nakabayashi, Kazumasa Nomura, Kazuhiko Ohno, Toshio Kondo:
Design and evaluation of fine-grain-mode transition method based on dynamic memory access analysing for variable stages pipeline processor. 41-47 - Cheng-Chi Lee, Chi-Tung Chen, Ping-Hsien Wu, Te-Yu Chen:
Three-factor control protocol based on elliptic curve cryptosystem for universal serial bus mass storage devices. 48-56
Volume 7, Number 2, March 2013
- Alessandro Strano, Nicola Caselli, Simone Terenzi, Davide Bertozzi:
Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip. - Mario Lodde, Antoni Roca, José Flich:
Built-in fast gather control network for efficient support of coherence protocols. - Ana Jokanovic, José Carlos Sancho, Germán Rodríguez, Cyriel Minkenberg, Ramón Beivide, Jesús Labarta:
On the trade-off of mixing scientific applications on capacity high-performance computing systems. - Arseniy Vitkovskiy, Vassos Soteriou, Chrysostomos Nicopoulos:
Dynamic fault-tolerant routing algorithm for networks-on-chip based on localised detouring paths.
Volume 7, Number 3, May 2013
- Sanaz Azampanah, Ahmad Khademzadeh, Nader Bagherzadeh, Majid Janidarmian, Reza Shojaee:
Contention-aware selection strategy for application-specific network-on-chip. - Kier Dugan, Jeffrey S. Reeve, Andrew D. Brown, Stephen B. Furber:
Interconnection system for the spiNNaker biologically inspired multi-computer. - Shervin Vakili, J. M. Pierre Langlois, Guy Bois:
Customised soft processor design: a compromise between architecture description languages and parameterisable processors. - T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi:
Single-configuration fault detection in applicationdependent testing of field programmable gate array interconnects.
Volume 7, Number 4, July 2013
- Han-Yee Kim, Young-Hwan Kim, Heon-Chang Yu, Taeweon Suh:
Performance evaluation of many-core systems: case study with TILEPro64. 143-154 - Ons Mbarek, Alain Pegatoquet, Michel Auguin:
Power domain management interface: flexible protocol interface for transaction-level power domain management. 155-166 - Mohammad Hossein Moaiyeri, Reza Faghih Mirzaee, Akbar Doostaregan, Keivan Navi, Omid Hashemipour:
A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits. 167-181 - Irith Pomeranz:
On multi-cycle test cubes. 182-189
Volume 7, Number 5, September 2013
- Erfan Azarkhish, Igor Loi, Luca Benini:
A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects. 191-199 - Laurentiu Acasandrei, Angel Barriga:
AMBA bus hardware accelerator IP for Viola-Jones face detection. 200-209 - Nachiketa Das, Pranab Roy, Hafizur Rahaman:
Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate arrays. 210-220 - Kiran Kumar Anumandla, Rangababu Peesapati, Samrat L. Sabat, Siba K. Udgata, Ajith Abraham:
Field programmable gate arrays-based differential evolution coprocessor: a case study of spectrum allocation in cognitive radio network. 221-234
Volume 7, Number 6, November 2013
- Fatemeh Khalili, Hamid R. Zarandi:
A fault-tolerant core mapping technique in networks-on-chip. 238-245 - Luigi Pomante:
HW/SW co-design of dedicated heterogeneous parallel systems: an extended design space exploration approach. 246-254 - Nizar Dahir, Terrence S. T. Mak, Ra'ed Al-Dujaily, Alex Yakovlev:
Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip. 255-263 - Masoumeh Ebrahimi:
Fully adaptive routing algorithms and region-based approaches for two-dimensional and three-dimensional networks-on-chip. 264-273 - Neda Hassanpour, Shaahin Hessabi, Parisa Khadem Hamedani:
Temperature control in three-network on chips using task migration. 274-281 - Ahmed A. Morgan, Haytham Elmiligi, M. Watheq El-Kharashi, Fayez Gebali:
Unified multi-objective mapping and architecture customisation of networks-on-chip. 282-293 - Ammar Karkar, Janice E. Turner, Kenneth Tong, Ra'ed Al-Dujaily, Terrence S. T. Mak, Alex Yakovlev, Fei Xia:
Hybrid wire-surface wave interconnects for next-generation networks-on-chip. 294-303 - Arpit Joshi, Prasanna Venkatesh Rengasamy, Madhu Mutyam:
Prevention slot flow-control mechanism for low latency torus network-on-chip. 304-316
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