• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 53 matches

• 2017
• 
  Fredy Augusto M. Alves, Peter Jamieson, Lucas B. da Silva, Ricardo S. Ferreira, José Augusto Miranda Nacif:
  Designing a collision detection accelerator on a heterogeneous CPU-FPGA platform. ReConFig 2017: 1-6
• 
  Ian J. Barge, Cristinel Ababei:
  H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip. ReConFig 2017: 1-6
• 
  Christopher Blochwitz, Raphael Klink, Jan Moritz Joseph, Thilo Pionteck:
  Continuous live-tracing as debugging approach on FPGAs. ReConFig 2017: 1-8
• 
  Andrew Boutros, Brett Grady, Mustafa Abbas, Paul Chow:
  Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis. ReConFig 2017: 1-6
• 
  Anthony Brandon, Michael Trimarchi:
  Trusted display and input using screen overlays. ReConFig 2017: 1-6
• 
  Pedro Bruel, Alfredo Goldman, Sai Rahul Chalamalasetti, Dejan S. Milojicic:
  Autotuning high-level synthesis for FPGAs using OpenTuner and LegUp. ReConFig 2017: 1-6
• 
  Qianqiao Chen, Vaibhawa Mishra, José L. Núñez-Yáñez, Georgios Zervas:
  Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources. ReConFig 2017: 1-6
• 
  Young H. Cho, Siddharth S. Bhargav:
  Fine-grained on-line power monitoring for soft microprocessor based system-on-chip. ReConFig 2017: 1-6
• 
  Sreeja Chowdhury, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte:
  Aging resilient RO PUF with increased reliability in FPGA. ReConFig 2017: 1-7
• 
  Girish Deshpande, Dinesh K. Bhatia:
  Microchannels for thermal management in FPGAs. ReConFig 2017: 1-5
• 
  William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj:
  Side-channel resistant soft core processor for lightweight block ciphers. ReConFig 2017: 1-8
• 
  Tobias Drewes, Jan Moritz Joseph, Thilo Pionteck:
  An FPGA-based prototyping framework for Networks-on-Chip. ReConFig 2017: 1-7
• 
  Andreas Engel, Andreas Koch:
  Energy-efficient reconfiguration of flash-based FPGAs in heterogeneous wireless sensor nodes. ReConFig 2017: 1-8
• 
  Farnoud Farahmand, Ahmed Ferozpuri, William Diehl, Kris Gaj:
  Minerva: Automated hardware optimization tool. ReConFig 2017: 1-8
• 
  Umer Farooq, Habib Mehrez, Muhammad Khurram Bhatti:
  Comparison of direct and switch-based inter-FPGA routing interconnect for multi-FPGA systems. ReConFig 2017: 1-6
• 
  Bernard Girau, César Torres-Huitzil:
  Optimal weight storage improves fault tolerance of SOMs. ReConFig 2017: 1-6
• 
  Muhammad K. A. Hamdan, Diane T. Rover:
  VHDL generator for a high performance convolutional neural network FPGA-based accelerator. ReConFig 2017: 1-6
• 
  Tripti Jain, Klaus Schneider, Ankesh Jain:
  Deriving concentrators from binary sorters using half cleaners. ReConFig 2017: 1-6
• 
  Benedikt Janßen, Fatih Korkmaz, Halil Derya, Michael Hübner, Mário Lopes Ferreira, João Canas Ferreira:
  Towards a type 0 hypervisor for dynamic reconfigurable systems. ReConFig 2017: 1-7
• 
  Jan Moritz Joseph, Morten Mey, Kristian Ehlers, Christopher Blochwitz, Tobias Winker, Thilo Pionteck:
  Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS. ReConFig 2017: 1-8
• 
  Ievgen Kabin, Zoya Dyka, Dan Kreiser, Peter Langendörfer:
  Horizontal address-bit DPA against montgomery kP implementation. ReConFig 2017: 1-8
• 
  Rasha Karakchi, Lothrop O. Richards, Jason D. Bakos:
  A Dynamically Reconfigurable Automata Processor Overlay. ReConFig 2017: 1-8
• 
  David C. Keezer, Jingchi Yang:
  Biologically inspired hierarchical structure for self-repairing FPGAs. ReConFig 2017: 1-8
• 
  Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano:
  Glitch-aware variable pipeline optimization for CGRAs. ReConFig 2017: 1-6
• 
  Joao Lopes, Diogo Sousa, João Canas Ferreira:
  Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices. ReConFig 2017: 1-7
• 
  Pongstorn Maidee, Alireza Kaviani, Kevin Zeng:
  LinkBlaze: Efficient global data movement for FPGAs. ReConFig 2017: 1-8
• 
  Hiroki Nakamura, Hirotaka Takayama, Yoshiki Yamaguchi, Taisuke Boku:
  Thorough analysis of PCIe Gen3 communication. ReConFig 2017: 1-6
• 
  Daniel H. Noronha, Jose P. Pinilla, Steven J. E. Wilton:
  Rapid circuit-specific inlining tuning for FPGA high-level synthesis. ReConFig 2017: 1-6
• 
  Michele Paolino, Sebastien Pinneterre, Daniel Raho:
  FPGA virtualization with accelerators overcommitment for network function virtualization. ReConFig 2017: 1-6
• 
  Diogo Parrinha, Ricardo Chaves:
  Flexible and low-cost HSM based on non-volatile FPGAs. ReConFig 2017: 1-8

skipping 23 more matches