• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 41 matches

• 2000
• 
  Elias Ahmed, Jonathan Rose:
  The effect of LUT and cluster size on deep-submicron FPGA performance and density. FPGA 2000: 3-12
• 
  Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami:
  Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract). FPGA 2000: 218
• 
  V. S. Balakrishnan, Hardy J. Pottinger, Fikret Erçal, Mukesh Agarwal:
  Design and implementation of an FPGA based processor for compressed images (poster abstract). FPGA 2000: 218
• 
  Vaughn Betz, Jonathan Rose:
  Automatic generation of FPGA routing architectures from high-level descriptions. FPGA 2000: 175-184
• 
  Ian Brynjolfson, Zeljko Zilic:
  FPGA clock management for low power applications (poster abstract). FPGA 2000: 219
• 
  Pak K. Chan, Martine D. F. Schlag:
  New parallelization and convergence results for NC: a negotiation-based FPGA router. FPGA 2000: 165-174
• 
  Jason Cong, Hui Huang, Xin Yuan:
  Technology mapping for k/m-macrocell based FPGAs. FPGA 2000: 51-59
• 
  Jason Cong, Kenneth Yan:
  Synthesis for FPGAs with embedded memory blocks. FPGA 2000: 75-82
• 
  Adam J. Elbirt, Christof Paar:
  An FPGA implementation and performance evaluation of the Serpent block cipher. FPGA 2000: 33-40
• 
  William Fornaciari, Vincenzo Piuri, Luigi Ripamonti:
  Virtualization of FPGA via segmentation (poster abstract). FPGA 2000: 222
• 
  Andrés D. García, Jean-Luc Danger, Wayne P. Burleson:
  Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. FPGA 2000: 220
• 
  Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
  Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract). FPGA 2000: 222
• 
  Frank Heile, Andrew Leaver, Kerry Veenstra:
  Programmable memory blocks supporting content-addressable memory. FPGA 2000: 13-21
• 
  Lorenz Huelsbergen:
  A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms. FPGA 2000: 105-115
• 
  Piyush Jamkhandi, Amar Mukherjee, Kunal Mukherjee, Robert Franceschini:
  Novel hardware-software architecture for the recursive merge filtering algorithm (poster abstract). FPGA 2000: 220
• 
  Alireza Kaviani, Stephen Dean Brown:
  Technology mapping issues for an FPGA with lookup tables and PLA-like blocks. FPGA 2000: 60-66
• 
  Hea Joung Kim, William H. Mangione-Smith:
  Factoring large numbers with programmable hardware. FPGA 2000: 41-48
• 
  Huesung Kim, Arun K. Somani, Akhilesh Tyagi:
  A reconfigurable multi-function computing cache architecture. FPGA 2000: 85-94
• 
  S. Kumar, Luiz Pires, Subburajan Ponnuswamy, C. Nanavati, J. Golusky, M. Vojta, S. Wadi, D. Pandalai, Henk A. E. Spaanenburg:
  A benchmark suite for evaluating configurable computing systems--status, reflections, and future directions. FPGA 2000: 126-134
• 
  Vijay Lakamraju, Russell Tessier:
  Tolerating operational faults in cluster-based FPGAs. FPGA 2000: 187-194
• 
  Hyuk-Jun Lee, Michael J. Flynn:
  Coarse-grained carry architecture for FPGA (poster abstract). FPGA 2000: 217
• 
  Guy G. Lemieux, Paul Leventis, David M. Lewis:
  Generating highly-routable sparse crossbars for PLDs. FPGA 2000: 155-164
• 
  Yu-Chung Lin, Su-Feng Tseng, Tsai-Ming Hsieh:
  Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract). FPGA 2000: 217
• 
  John W. Lockwood, Jonathan S. Turner, David E. Taylor:
  Field programmable port extender (FPX) for distributed routing and queuing. FPGA 2000: 137-144
• 
  Alexander Marquardt, Vaughn Betz, Jonathan Rose:
  Timing-driven placement for FPGAs. FPGA 2000: 203-213
• 
  Rob McCready, Jonathan Rose:
  Real-time, frame-rate face detection on a configurable hardware system (poster abstract). FPGA 2000: 221
• 
  F. S. Ogrenci, Aggelos K. Katsaggelos, Majid Sarrafzadeh:
  FPGA implementation and analysis of image restoration. FPGA 2000: 219
• 
  Abdelkrim Kamel Oudjida, Sabrina Titri, Mustapha Hamerlain:
  Synthesizing full-systolic arrays for matrix product on Xilinx's XC4000(E, EX) FPGAs (poster abstract). FPGA 2000: 222
• 
  Eric K. Pauer, Paul D. Fiore, John M. Smith, Cory S. Myers:
  Algorithm analysis and mapping environment for adaptive computing systems (poster abstract). FPGA 2000: 217
• 
  Herman Schmit, Ray Andraka, Philip Friedin, Satnam Singh, Tim Southgate:
  The John Henry Syndrome (panel session)(abstract only): humans vs. machines as FPGA designers. FPGA 2000: 101

skipping 11 more matches