• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
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  e.g., graph$ matches "graph", but not "graphics"
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Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 23 matches

• 1995
• 
  Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas:
  New CMOS VLSI linear self-timed architectures. ASYNC 1995: 14-23
• 
  D. K. Arvind, Robert D. Mullins, Vinod E. F. Rebello:
  Micronets: a model for decentralising control in asynchronous processor architectures. ASYNC 1995: 190-199
• 
  Andrew M. Bailey, Mark B. Josephs:
  Sequencer circuits for VLSI programming. ASYNC 1995: 82-90
• 
  Kees van Berkel, Ronan Burgess, Joep L. W. Kessels, Ad M. G. Peeters, Marly Roncken, Frits D. Schalij, Rik van de Wiel:
  A single-rail re-implementation of a DCC error detector using a generic standard-cell library. ASYNC 1995: 72-
• 
  Kees van Berkel, Ferry Huberts, Ad M. G. Peeters:
  Stretching quasi delay insensitivity by means of extended isochronic forks. ASYNC 1995: 99-
• 
  Janusz A. Brzozowski, Kaamran Raahemifar:
  Testing C-elements is not elementary. ASYNC 1995: 150-159
• 
  Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu:
  ARAS: asynchronous RISC architecture simulator. ASYNC 1995: 210-
• 
  C. J. Elston, D. B. Christianson, Paul A. Findlay, Gordon B. Steven:
  Hades-towards the design of an asynchronous superscalar processor. ASYNC 1995: 200-209
• 
  Craig Farnsworth, David A. Edwards, Jianwei Liu, Shiv S. Sikand:
  A hybrid asynchronous system design environment. ASYNC 1995: 91-98
• 
  Eckhard Grass, Simon Jones:
  Asynchronous circuits based on multiple localised current-sensing completion detection. ASYNC 1995: 170-
• 
  David A. Kearney, Neil W. Bergmann:
  Performance evaluation of asynchronous logic pipelines with data dependent processing delays. ASYNC 1995: 4-13
• 
  Joep L. W. Kessels:
  VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player. ASYNC 1995: 44-52
• 
  Ajay Khoche, Erik Brunvand:
  Testing self-timed circuits using partial scan. ASYNC 1995: 160-169
• 
  Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt:
  ECSTAC: a fast asynchronous microprocessor. ASYNC 1995: 180-189
• 
  Chris J. Myers, Peter A. Beerel, Teresa H.-Y. Meng:
  Technology mapping of timed circuits. ASYNC 1995: 138-
• 
  Radu Negulescu, Janusz A. Brzozowski:
  Relative liveness: from intuition to automated verification. ASYNC 1995: 108-117
• 
  Ad M. G. Peeters, Kees van Berkel:
  Single-rail handshake circuits. ASYNC 1995: 53-62
• 
  Oriol Roig, Jordi Cortadella, Enric Pastor:
  Hierarchical gate-level verification of speed-independent circuits. ASYNC 1995: 128-137
• 
  Rik van de Wiel:
  High-level test evaluation of asynchronous circuits. ASYNC 1995: 63-71
• 
  Alexandre Yakovlev, Victor Varshavsky, Vyacheslav Marakhovsky, Alexei L. Semenov:
  Designing an asynchronous pipeline token ring interface. ASYNC 1995: 32-
• 
  Jelio Todorov Yantchev, C. G. Huang, Mark B. Josephs, Ivailo M. Nedelchev:
  Low-latency asynchronous FIFO buffers. ASYNC 1995: 24-31
• 
  Chantal Ykman-Couvreur, Bill Lin:
  Optimised state assignment for asynchronous circuit synthesis. ASYNC 1995: 118-127
• 
  Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK. IEEE Computer Society 1995, ISBN 0-8186-7098-3 [contents]