- Weiyun Lu, Martin Radetzki:
Efficient Fault Simulation of SystemC Designs. DSD 2011: 487-494 - Mohammad Maghsoudloo, Hamid R. Zarandi, Saadat Pour-Mozafari, Navid Khoshavi:
Soft Error Detection Technique in Multi-threaded Architectures Using Control-Flow Monitoring. DSD 2011: 789-792 - Paolo Maistri, Régis Leveugle:
10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard. DSD 2011: 266-269 - Takieddine Majdoub, Sébastien Le Nours, Olivier Pasquier, Fabienne Nouvel:
Transaction Level Modeling of a Networked Embedded System Based on a Power Line Communication Protocol. DSD 2011: 438-441 - Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer:
A Cost Effective Centralized Adaptive Routing for Networks-on-Chip. DSD 2011: 39-46 - Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas:
An Enhanced Path Delay Fault Simulator for Combinational Circuits. DSD 2011: 375-381 - Guido Matrella, Davide Marani:
An Embedded Video Sensor for a Smart Traffic Light. DSD 2011: 769-776 - Pedro Miguens Matutino, Ricardo Chaves, Leonel Sousa:
Binary-to-RNS Conversion Units for moduli {2n ± 3}. DSD 2011: 460-467 - Cor Meenderinck, Ben H. H. Juurlink:
Nexus: Hardware Support for Task-Based Programming. DSD 2011: 442-445 - Daniel Mueller-Gritschneder, Kun Lu, Ulf Schlichtmann:
Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level. DSD 2011: 600-607 - Abdul Naeem, Axel Jantsch, Xiaowen Chen, Zhonghai Lu:
Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems. DSD 2011: 47-54 - A. N. Nagamani, S. Nishchai:
Quaternary High Performance Arithmetic Logic Unit Design. DSD 2011: 148-153 - Satoru Nakano, Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi:
A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations. DSD 2011: 701-707 - Yohei Nakata, Yukihiro Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers. DSD 2011: 801-804 - Ghazaleh Nazarian, Christos Strydis, Georgi Gaydadjiev:
Compatibility Study of Compile-Time Optimizations for Power and Reliability. DSD 2011: 809-813 - Mohammad Hossein Neishaburi, Zeljko Zilic:
On Failure Rate Assessment Using an Executable Model of the System. DSD 2011: 29-36 - Ashkan Beyranvand Nejad, Anca Mariana Molnos, Kees Goossens:
A Unified Execution Model for Data-Driven Applications on a Composable MPSoC. DSD 2011: 818-822 - Andrew Nelson, Orlando Moreira, Anca Mariana Molnos, Sander Stuijk, Ba Thang Nguyen, Kees Goossens:
Power Minimisation for Real-Time Dataflow Applications. DSD 2011: 117-124 - Alexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, Felipe M. G. França:
Hardware Reuse in Modern Application-Specific Processors and Accelerators. DSD 2011: 140-147 - Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak:
A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations. DSD 2011: 511-518 - Sergey Ostroumov, Leonidas Tsiopoulos:
VHDL Code Generation from Formal Event-B Models. DSD 2011: 127-134 - Tolga Ovatman, Feza Buzluca:
Model Driven Cache-Aware Scheduling of Object Oriented Software for Chip Multiprocessors. DSD 2011: 719-726 - Tevfik Zafer Ozcan, Cagla Cakir, Mert Cetin, Ilker Hamzaoglu:
An Overlapped Block Motion Compensation Hardware for Frame Rate Conversion. DSD 2011: 309-315 - Thomas Plos, Martin Feldhofer:
Hardware Implementation of a Flexible Tag Platform for Passive RFID Devices. DSD 2011: 293-300 - Romain Prolonge, Fabien Clermidy, Leonel Tedesco, Fernando Moraes:
Dynamic Flow Reconfiguration Strategy to Avoid Communication Hot-Spots. DSD 2011: 519-524 - George Provelengios, Nikolaos S. Voros, Paris Kitsos:
Low Power FPGA Implementations of JH and Fugue Hash Functions. DSD 2011: 417-421 - Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture. DSD 2011: 173-180 - Alireza Rohani, Hans G. Kerkhoff:
A Technique for Accelerating Injection of Transient Faults in Complex SoCs. DSD 2011: 213-220 - Michal Rumplík, Josef Strnadel:
On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits. DSD 2011: 367-374 - Richard Ruzicka, Václav Simek:
Chip Temperature Selfregulation for Digital Circuits Using Polymorphic Electronics Principles. DSD 2011: 205-212