"An Enhanced Path Delay Fault Simulator for Combinational Circuits."

Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas (2011)

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DOI: 10.1109/DSD.2011.52

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-06

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  - https://dblp.org/rec/conf/dsd/ManikandanLA11
Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas:
An Enhanced Path Delay Fault Simulator for Combinational Circuits. DSD 2011: 375-381

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