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@article{DBLP:journals/integration/BiswasCPD17,
  author       = {Achira Pal and
                  Atal Chaudhuri and
                  Rajat Kumar Pal and
                  Alak Kumar Datta},
  title        = {Hardness of crosstalk minimization in two-layer channel routing},
  journal      = {Integr.},
  volume       = {56},
  pages        = {139--147},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.10.001},
  doi          = {10.1016/J.VLSI.2016.10.001},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/BiswasCPD17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/ChenGZW17,
  author       = {Jun Chen and
                  Benqing Guo and
                  Boyang Zhang and
                  Guangjun Wen},
  title        = {An inductorless wideband common-gate {LNA} with dual capacitor cross-coupled
                  feedback and negative impedance techniques},
  journal      = {Integr.},
  volume       = {56},
  pages        = {53--60},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.09.006},
  doi          = {10.1016/J.VLSI.2016.09.006},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/ChenGZW17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/CuiLLQ17,
  author       = {Aijiao Cui and
                  Yanhui Luo and
                  Huawei Li and
                  Gang Qu},
  title        = {Why current secure scan designs fail and how to fix them?},
  journal      = {Integr.},
  volume       = {56},
  pages        = {105--114},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.10.011},
  doi          = {10.1016/J.VLSI.2016.10.011},
  timestamp    = {Thu, 11 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/CuiLLQ17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/DehbashianM17,
  author       = {Maryam Dehbashian and
                  Mohammad Maymandi{-}Nejad},
  title        = {A new hybrid algorithm for analog ICs optimization based on the shrinking
                  circles technique},
  journal      = {Integr.},
  volume       = {56},
  pages        = {148--166},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.09.009},
  doi          = {10.1016/J.VLSI.2016.09.009},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/DehbashianM17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/El-Maleh17,
  author       = {Aiman H. El{-}Maleh},
  title        = {A probabilistic pairwise swap search state assignment algorithm for
                  sequential circuit optimization},
  journal      = {Integr.},
  volume       = {56},
  pages        = {32--43},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.08.001},
  doi          = {10.1016/J.VLSI.2016.08.001},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/El-Maleh17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/EwetzK17,
  author       = {Rickard Ewetz and
                  Cheng{-}Kok Koh},
  title        = {Fast clock scheduling and an application to clock tree synthesis},
  journal      = {Integr.},
  volume       = {56},
  pages        = {115--127},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.10.012},
  doi          = {10.1016/J.VLSI.2016.10.012},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/EwetzK17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/FreyY17,
  author       = {Jonathan Frey and
                  Qiaoyan Yu},
  title        = {A hardened network-on-chip design using runtime hardware Trojan mitigation
                  methods},
  journal      = {Integr.},
  volume       = {56},
  pages        = {15--31},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.06.008},
  doi          = {10.1016/J.VLSI.2016.06.008},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/FreyY17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/GuoS17,
  author       = {Xinfei Guo and
                  Mircea R. Stan},
  title        = {Implications of accelerated self-healing as a key design knob for
                  cross-layer resilience},
  journal      = {Integr.},
  volume       = {56},
  pages        = {167--180},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.10.008},
  doi          = {10.1016/J.VLSI.2016.10.008},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/GuoS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/HoAK17,
  author       = {Patrick W. C. Ho and
                  Haider Abbas F. Almurib and
                  T. Nandha Kumar},
  title        = {Configurable memristive logic block for memristive-based {FPGA} architectures},
  journal      = {Integr.},
  volume       = {56},
  pages        = {61--69},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.09.003},
  doi          = {10.1016/J.VLSI.2016.09.003},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/HoAK17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/KaboliGA17,
  author       = {Milad Kaboli and
                  Behzad Ghanavati and
                  Majid Akhlaghi},
  title        = {A new {CMOS} pseudo approximation exponential function generator by
                  modified particle swarm optimization algorithm},
  journal      = {Integr.},
  volume       = {56},
  pages        = {70--76},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.10.003},
  doi          = {10.1016/J.VLSI.2016.10.003},
  timestamp    = {Mon, 28 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/KaboliGA17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/KimK17,
  author       = {Joohan Kim and
                  Taewhan Kim},
  title        = {Boundary optimization of buffered clock trees for low power},
  journal      = {Integr.},
  volume       = {56},
  pages        = {86--95},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.10.004},
  doi          = {10.1016/J.VLSI.2016.10.004},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/KimK17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/LiuGPH17,
  author       = {Tao Liu and
                  Hui Guo and
                  Sri Parameswaran and
                  Xiaobo Sharon Hu},
  title        = {iCETD: An improved tag generation design for memory data authentication
                  in embedded processor systems},
  journal      = {Integr.},
  volume       = {56},
  pages        = {96--104},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.10.006},
  doi          = {10.1016/J.VLSI.2016.10.006},
  timestamp    = {Fri, 09 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/LiuGPH17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/MitraN17,
  author       = {Jubin Mitra and
                  Tapan Kumar Nayak},
  title        = {Reconfigurable very high throughput low latency {VLSI} {(FPGA)} design
                  architecture of {CRC} 32},
  journal      = {Integr.},
  volume       = {56},
  pages        = {1--14},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.09.005},
  doi          = {10.1016/J.VLSI.2016.09.005},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/MitraN17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Papakonstantinou17,
  author       = {George K. Papakonstantinou},
  title        = {Exclusive or Sum of Complex Terms expressions minimization},
  journal      = {Integr.},
  volume       = {56},
  pages        = {44--52},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.08.005},
  doi          = {10.1016/J.VLSI.2016.08.005},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Papakonstantinou17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/ShahghasemiY17,
  author       = {Mohsen Shahghasemi and
                  Mohammad Yavari},
  title        = {{MASH} {\(\Sigma\)}{\(\Delta\)} modulators with a noise-shaped two-step
                  {ADC} in the second stage},
  journal      = {Integr.},
  volume       = {56},
  pages        = {77--85},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.10.002},
  doi          = {10.1016/J.VLSI.2016.10.002},
  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/ShahghasemiY17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/SorkhabiZ17,
  author       = {Samin Ebrahim Sorkhabi and
                  Lihong Zhang},
  title        = {Automated topology synthesis of analog and {RF} integrated circuits:
                  {A} survey},
  journal      = {Integr.},
  volume       = {56},
  pages        = {128--138},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.vlsi.2016.10.017},
  doi          = {10.1016/J.VLSI.2016.10.017},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/SorkhabiZ17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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