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@inproceedings{DBLP:conf/hldvt/0001BFS17,
  author       = {Binod Kumar and
                  Kanad Basu and
                  Masahiro Fujita and
                  Virendra Singh},
  title        = {{RTL} level trace signal selection and coverage estimation during
                  post-silicon validation},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {59--66},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167464},
  doi          = {10.1109/HLDVT.2017.8167464},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/0001BFS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/AmirG17,
  author       = {Maral Amir and
                  Tony Givargis},
  title        = {{HES} machine: Harmonic equivalent state machine modeling for cyber-physical
                  systems},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {31--38},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167460},
  doi          = {10.1109/HLDVT.2017.8167460},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/AmirG17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/BalkovskiH17,
  author       = {Sophia Balkovski and
                  Ian G. Harris},
  title        = {Designing cyber-physical systems from natural language descriptions},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {39--44},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167461},
  doi          = {10.1109/HLDVT.2017.8167461},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/BalkovskiH17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/BarashF17,
  author       = {Guy Barash and
                  Eitan Farchi},
  title        = {A randomized algorithm for constructing cross-feature tests from single
                  feature tests},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {1--8},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167456},
  doi          = {10.1109/HLDVT.2017.8167456},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/BarashF17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/ChengSLD17,
  author       = {Zhongqi Cheng and
                  Tim Schmidt and
                  Guantao Liu and
                  Rainer D{\"{o}}mer},
  title        = {Thread- and data-level parallel simulation in SystemC, a Bitcoin miner
                  case study},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {74--81},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167466},
  doi          = {10.1109/HLDVT.2017.8167466},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/ChengSLD17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/DemroziZP17,
  author       = {Florenc Demrozi and
                  Riccardo Zucchelli and
                  Graziano Pravadelli},
  title        = {Exploiting sub-graph isomorphism and probabilistic neural networks
                  for the detection of hardware Trojans at {RTL}},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {67--73},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167465},
  doi          = {10.1109/HLDVT.2017.8167465},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/DemroziZP17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/DevarajegowdaE17,
  author       = {Keerthikumara Devarajegowda and
                  Wolfgang Ecker},
  title        = {On generation of properties from specification},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {95--98},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167470},
  doi          = {10.1109/HLDVT.2017.8167470},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/DevarajegowdaE17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/Fujita17,
  author       = {Masahiro Fujita},
  title        = {An approach to approximate computing: Logic transformations for one-minterm
                  changes in specification},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {91--94},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167469},
  doi          = {10.1109/HLDVT.2017.8167469},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/Fujita17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/Lora17,
  author       = {Michele Lora},
  title        = {Validation of {HMI} applications for industrial smart display},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {23--30},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167459},
  doi          = {10.1109/HLDVT.2017.8167459},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/Lora17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/MadaniKDBB17,
  author       = {Siroos Madani and
                  Kasem Khalil and
                  Bappaditya Dey and
                  Devante Bonton and
                  Magdy A. Bayoumi},
  title        = {Repair techniques for aged TSVs in 3D integrated circuits},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {53--58},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167463},
  doi          = {10.1109/HLDVT.2017.8167463},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/MadaniKDBB17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/MoharikarG17,
  author       = {Pankaj Moharikar and
                  Jayakrishna Guddeti},
  title        = {Automated test generation for post silicon microcontroller validation},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {45--52},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167462},
  doi          = {10.1109/HLDVT.2017.8167462},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/MoharikarG17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/RoyH17,
  author       = {Tonmoy Roy and
                  Michael Hsiao},
  title        = {Reachability analysis in {RTL} circuits using k-induction bounded
                  model checking},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {9--16},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167457},
  doi          = {10.1109/HLDVT.2017.8167457},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/RoyH17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/ShirmohammadiSM17,
  author       = {Zahra Shirmohammadi and
                  Hadi Zamani Sabzi and
                  Seyed Ghassem Miremadi},
  title        = {3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk
                  faults in 3D ICs},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {87--90},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167468},
  doi          = {10.1109/HLDVT.2017.8167468},
  timestamp    = {Mon, 26 Jun 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/hldvt/ShirmohammadiSM17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/VenutoMG17,
  author       = {Daniela De Venuto and
                  Giovanni Mezzina and
                  V. L. Gallo},
  title        = {Design and implementation of FPGA-based muscle conduction velocity
                  tracker in dynamic contractions during the gait},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {82--86},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167467},
  doi          = {10.1109/HLDVT.2017.8167467},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/VenutoMG17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/ZokaeeBJBN17,
  author       = {Farzaneh Zokaee and
                  Hossein Sabaghian Bidgoli and
                  Vahid Janfaza and
                  Payman Behnam and
                  Zainalabedin Navabi},
  title        = {A novel SAT-based {ATPG} approach for transition delay faults},
  booktitle    = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  pages        = {17--22},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HLDVT.2017.8167458},
  doi          = {10.1109/HLDVT.2017.8167458},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/ZokaeeBJBN17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/hldvt/2017,
  title        = {2017 {IEEE} International High Level Design Validation and Test Workshop,
                  {HLDVT} 2017, Santa Cruz, CA, USA, October 5-6, 2017},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://ieeexplore.ieee.org/xpl/conhome/8119415/proceeding},
  isbn         = {978-1-5090-3997-5},
  timestamp    = {Wed, 16 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/hldvt/2017.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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