"Optimizing FPGA Logic Block Architectures for Arithmetic."

Kevin E. Murray et al. (2020)

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DOI: 10.1109/TVLSI.2020.2965772

access: closed

type: Journal Article

metadata version: 2020-08-06

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  - https://dblp.org/rec/journals/tvlsi/MurrayLWMWHYCKA20
Kevin E. Murray, Jason Luu, Matthew J. P. Walker, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz:
Optimizing FPGA Logic Block Architectures for Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 28(6): 1378-1391 (2020)

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